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path: root/drivers/gpu
AgeCommit message (Expand)Author
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/amdgpu: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian
2025-11-18drm/xe/vf: Shadow buffer management for CCS read/write operationsSatyanarayana K V P
2025-11-18drm/xe/sa: Shadow buffer support in the sub-allocator poolSatyanarayana K V P
2025-11-18drm/xe/irq: Handle msix vector0 interruptVenkata Ramana Nayana
2025-11-18drm/xe: Remove duplicate DRM_EXEC selection from KconfigShuicheng Lin
2025-11-18drm/xe/kunit: Fix forcewake assertion in mocs testMatt Roper
2025-11-18drm/xe: Prevent BIT() overflow when handling invalid prefetch regionShuicheng Lin
2025-11-18drm/radeon: delete radeon_fence_process in is_signaled, no deadlockRobert McClinton
2025-11-18drm/amd/display: Fix pbn to kbps ConversionFangzhi Zuo
2025-11-18drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5Ivan Lipski
2025-11-18drm/amd/display: Add an HPD filter for HDMIIvan Lipski
2025-11-18drm/amd/display: Increase DPCD read retriesMario Limonciello (AMD)
2025-11-18drm/msm/a8xx: Add support for Adreno X2-85 GPUAkhil P Oommen
2025-11-18drm/msm/adreno: Do CX GBIF config before GMU startAkhil P Oommen
2025-11-18drm/msm/a8xx: Add support for Adreno 840 GPUAkhil P Oommen
2025-11-18drm/msm/adreno: Support AQE engineAkhil P Oommen
2025-11-18drm/msm/adreno: Introduce A8x GPU SupportAkhil P Oommen
2025-11-18drm/msm/a6xx: Share dependency vote table with GMUAkhil P Oommen
2025-11-18drm/msm/a6xx: Improve MX rail fallback in RPMH vote initAkhil P Oommen
2025-11-18drm/msm/a8xx: Add support for A8x GMUAkhil P Oommen
2025-11-18drm/msm/a6xx: Rebase GMU register offsetsAkhil P Oommen
2025-11-18drm/msm/a6xx: Sync latest register definitionsAkhil P Oommen
2025-11-18drm/amd/display: Move sleep into each retry for retrieve_link_cap()Mario Limonciello (AMD)
2025-11-18drm/amd/display: Prevent Gating DTBCLK before It Is Properly LatchedFangzhi Zuo
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