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40 hoursMerge branch 'pinctrl-qcom/for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
40 hoursMerge branch 'renesas-pinctrl' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
40 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
40 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
42 hoursMerge branch 'pinctrl-qcom/for-current' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
4 dayspinctrl: upboard: add device id INTC1055 based UP boards supportGary Wang
Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data. Signed-off-by: Gary Wang <is0124@gmail.com> Reviewed-by: Thomas Richard <thomas.richard@bootlin.com> Acked-by: Linus Walleij <linusw@kernel.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
4 dayspinctrl: tigerlake: add some pin groups and functions for INTC1055Gary Wang
Add i2c0, i2c1, pwm0, uart1, ssp2 pin groups & functions in tgllp_soc_data for device id INTC1055. The pinctrl-upboard driver set the correct pin function corresponding to these data. Signed-off-by: Gary Wang <is0124@gmail.com> Acked-by: Linus Walleij <linusw@kernel.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
4 daysRevert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"Maulik Shah
This reverts commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-6-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
4 dayspinctrl: qcom: Acknowledge IRQs for PDC interrupt controllerStephan Gerhold
PDC needs to acknowledge incoming GPIO interrupts to clear the latched interrupt status in secondary mode of PDC. For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-5-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
9 daysMerge tag 'gpio-fixes-for-v7.2-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio fixes from Bartosz Golaszewski: - check the return value of gpiochip_add_data() in gpio-mvebu and gpio-htc-egpio - avoid locking context issues with GPIO drivers using the shared GPIO proxy by only allowing sleeping operations (atomic GPIO ops don't really make sense in shared context anyway) - with the above: restore non-sleeping GPIO access in pinctrl-meson - fix return value on OOM in gpio-timberdale - fix interrupt handling in gpio-mt7621 - support both A and B variants of NCT6126D in gpio-f7188x * tag 'gpio-fixes-for-v7.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: pinctrl: meson: restore non-sleeping GPIO access gpio: timberdale: Return -ENOMEM on dynamic memory allocation in probe gpio: mt7621: be sure IRQ domain is created before exposing GPIO chips gpio: mt7621: more robust management of IRQ domain teardown gpio: mt7621: avoid corruption of shared interrupt trigger state gpio: shared-proxy: always serialize with a sleeping mutex gpio-f7188x: Add support for NCT6126D version B gpio: htc-egpio: use managed gpiochip registration gpio: mvebu: fail probe if gpiochip registration fails
9 daysReplace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵Uwe Kleine-König (The Capable Hub)
files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
11 dayspinctrl: s32cc: implement GPIO functionalityAndrei Stefanescu
The updated SIUL2 block groups pinctrl, GPIO data access and interrupt control within the same hardware unit. The SIUL2 driver is therefore structured as a monolithic pinctrl/GPIO driver. GPIO data access and direction handling are implemented using the gpio-regmap library backed by a virtual regmap. The virtual regmap translates the gpio-regmap register model to the underlying SIUL2 registers: MSCR for direction, PGPDI for input values and PGPDO for output values. The existing pinctrl GPIO callbacks are used for the request/free path: they switch the pad to GPIO mode on request and restore the previous MSCR configuration when the GPIO is released. This change came as a result of upstream review in the following series: https://lore.kernel.org/linux-gpio/20260120115923.3463866-4-khristineandreea.barbulescu@oss.nxp.com/T/#m543c9edbdde74bdc68b6a2364e8b975356c33043 https://lore.kernel.org/all/20260504131148.3622697-7-khristineandreea.barbulescu@oss.nxp.com/ Support both SIUL2 DT layouts: - legacy pinctrl-only binding - extended pinctrl/GPIO/irqchip binding Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/linux-gpio/20260120115923.3463866-4-khristineandreea.barbulescu@oss.nxp.com/T/#m543c9edbdde74bdc68b6a2364e8b975356c33043 Link: https://lore.kernel.org/all/20260504131148.3622697-7-khristineandreea.barbulescu@oss.nxp.com/ Signed-off-by: Linus Walleij <linusw@kernel.org>
11 dayspinctrl: s32cc: change to "devm_pinctrl_register_and_init"Andrei Stefanescu
Switch from "devm_pinctrl_register" to "devm_pinctrl_register_and_init" and "pinctrl_enable" since this is the recommended way. Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
11 dayspinctrl: s32cc: remove inline specifiersKhristine Andreea Barbulescu
Remove unnecessary inline specifiers from static functions. Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
11 dayspinctrl: s32cc: add/fix some commentsKhristine Andreea Barbulescu
Add/fix some comments and print statements. Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
11 dayspinctrl: tb10x: Mark base as __iomemLinus Walleij
The compile tests are complaining that this is not correctly typed. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202606150641.cbQ05ZMM-lkp@intel.com/ Signed-off-by: Linus Walleij <linusw@kernel.org>
11 dayspinctrl: qcom: Add the tlmm driver for Maili platformJingyi Wang
Add support for Maili TLMM configuration and control via the pinctrl framework. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-2-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
11 dayspinctrl: meson: restore non-sleeping GPIO accessViacheslav Bocharov
Commit 28f240683871 ("pinctrl: meson: mark the GPIO controller as sleeping") set gpio_chip.can_sleep = true to work around gpio-shared-proxy holding a spinlock across a sleeping pinctrl config path. That locking bug is now fixed in the shared-proxy itself ("gpio: shared-proxy: always serialize with a sleeping mutex"), so the controller-wide workaround is no longer needed; the meson GPIO controller does not sleep. meson_gpio_get/set/direction_* access MMIO through regmap. The regmap_mmio bus uses fast I/O (spinlock) locking, so these value callbacks do not contain sleeping operations. Since gpio_chip.can_sleep describes the get/set value path, restore can_sleep = false. Marking the controller sleeping also broke atomic value consumers such as w1-gpio (1-Wire bitbang): w1_io.c runs its read time slot under local_irq_save() and uses the non-cansleep gpiod_set_value() / gpiod_get_value(), which with can_sleep=true trigger WARN_ON(can_sleep) in gpiolib on every transferred bit (from w1_gpio_write_bit() / w1_gpio_read_bit() via w1_reset_bus() and w1_search()). The printk and stack dump inside the IRQs-off, microsecond-scale time slot destroy the bit timing, so reset/presence detection and ROM search fail: the bus master registers but w1_master_slave_count stays at 0 and no devices are found. Verified on an Amlogic A113X board (DS18B20 on GPIOA_14): with can_sleep restored to false the warnings are gone and the sensor is detected and read again. This must not be applied or backported without the shared-proxy locking fix above; otherwise the original Khadas VIM3 splat returns on boards that genuinely share a meson GPIO. Fixes: 28f240683871 ("pinctrl: meson: mark the GPIO controller as sleeping") Link: https://lore.kernel.org/all/20260105150509.56537-1-bartosz.golaszewski@oss.qualcomm.com/ Signed-off-by: Viacheslav Bocharov <v@baodeep.com> Acked-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260625115718.1678991-3-v@baodeep.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
11 dayspinctrl: qcom: sc8280xp: Add missing wakeup entries for GPIO143/151Konrad Dybcio
Pins 143 and 151 were not included in the PDC wakeup map. They are normally used for PCIe2A and PCIe3a PERST# respectively, so they're unlikely to be excercised in practice, but still add them for the sake of completeness. Fixes: c0e4c71a9e7c ("pinctrl: qcom: Introduce sc8280xp TLMM driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260626-topic-8280_pinctrl_wakeup-v1-1-2ccb267148f5@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
12 dayspinctrl: qcom: Unconditionally mark gpio as wakeup enableSneh Mankad
GPIO interrupts that are wakeup capable need to be forwarded to wakeup capable parent irqchip. This is done via writing to it's wakeup_enable bit. Currently the bit is set only for PDC irqchip by checking skip_wake_irqs. skip_wake_irqs is set to differentiate between parent irqchips MPM and PDC. It is set when the parent irqchip is PDC to inform pinctrl about skipping the IRQ setting up at TLMM. However, the functionality to forward GPIO interrupts during SoC low power mode is needed regardless of which parent irqchip it is. Without the functionality it is impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260616-enable_wakeup_capable_gpios-v3-1-fb59647d89cb@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
12 dayspinctrl: qcom: Drop unused irq_data argument from ↵Hans de Goede
msm_gpio_update_dual_edge_pos() The "struct irq_data *d" argument to msm_gpio_update_dual_edge_pos() is unused, drop it. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260623122732.6439-2-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
12 dayspinctrl: qcom: Drop unnecessary bitmap_fill() callHans de Goede
Drop an unnecessary bitmap_fill() call from msm_gpio_irq_init_valid_mask(), this is unnecessary because gpiochip_allocate_mask() already does this. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260623122732.6439-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
12 dayspinctrl: qcom: spmi-gpio: Add PMG1110 GPIO supportFenglin Wu
Add PMG1110 GPIO support with its compatible string and match data. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260610-pmg1110-gpio-v1-2-a9c50cd8b5d9@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
12 dayspinctrl: bcm2835: Don't remove an unregistered GPIO chipDaniel McCarthy
If the devm_pinctrl_register() function fails, bcm2835_pinctrl_probe() calls gpiochip_remove() before gpiochip_add_data() has registered the GPIO chip. This means that upon failure the gpio_chip.gpiodev is NULL resulting in a null pointer dereference inside the gpiochip_remove() function. Remove the unnecessary function call to gpiochip_remove(). No GPIO cleanup is required because the GPIO chip has not yet been registered. Without this change there is potential for a kernel panic upon registration failure Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by: Daniel McCarthy <daniel@dragonzap.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
12 dayspinctrl: aspeed: Split TRST out of the AST2700 SoC1 JTAGM1 groupBilly Tsai
The JTAGM1 group includes the D12 ball carrying the TRST signal, but TRST is optional for a JTAG master and the ball may be needed for other functions on designs that do not wire it. With TRST embedded in the group, such designs cannot use the JTAG master at all. Move D12 into a new JTAGM1TRST group under the same JTAGM1 function so TRST is muxed only when a board requests it. Boards that do use TRST now need to select both the JTAGM1 and JTAGM1TRST groups. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
12 dayspinctrl: renesas: rza2: Embed pins in the priv structRosen Penev
Turn the separately allocated pinctrl_pin_desc array into a flexible array member of struct rza2_pinctrl_priv, annotated with __counted_by(npins). Compute the pin count before allocation so struct_size() can size the combined object, and the two allocations can be collapsed into one. Change npins to unsigned int to avoid potential overflow/underflow errors. Assisted-by: Claude:Opus-4.7 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260527202317.5347-1-rosenp@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
12 dayspinctrl: imx1: fix device_node leak in dt_is_flat_functions()Felix Gu
for_each_child_of_node() holds a reference on the iterator node that must be released on early return. imx1_pinctrl_dt_is_flat_functions() has two early return paths inside the loop that skip this cleanup. Replace both loops with the scoped variant so that the reference is automatically dropped when the iterator goes out of scope. Fixes: 63d2059cd665 ("pinctrl: imx1: Allow parsing DT without function nodes") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-26pinctrl: qcom: Avoid assigning unused private context in test casesSneh Mankad
tlmm_test_rising_while_disabled() sets thread_op_remain to 10, but this variable is only used by the threaded IRQ handler to control the number of GPIO pin toggles. Since tlmm_test_rising_while_disabled() does not register a threaded IRQ handler, the assignment is never used. Similarly, tlmm_test_high() and tlmm_test_low() set intr_op_remain to 9, but the variable is used to denote the IRQ handler the number of times GPIO signal has to be toggled from the hard IRQ handler. Since tlmm_test_high() and tlmm_test_low() themselves toggle the signal and do not require the hard IRQ handler to do it, the assignment is never used. Remove the thread_op_remain assignment from tlmm_test_rising_while_disabled() and intr_op_remain assignment from tlmm_test_high() and tlmm_test_low() test cases. This does not cause any change in functionality. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://patch.msgid.link/20260610-tlmm_test_changes-v2-1-f34536da4717@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-18Merge tag 'pinctrl-v7.2-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Add new generic callbacks to populate per-pin pin controllers creating groups and functions from the device tree building out pinctrl_generic_to_map() and move the Spacemit driver over to use this - Generic board-level pin control driver using the mux framework New pin controller drivers: - Amlogic (meson) A9 SoC - Aspeed AST2700 SoC0 and SoC1 - nVidia Tegra264 and Tegra238 - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM - Renesas RZ/G3L SoC - UltraRISC DP1000 Improvements: - Handle pull up/pull down properly in the Renesas RZG2L driver - Fix up nVidia Tegra 234 DT bindings - Fix up pin definitions in the Qualcomm Eliza driver - Qualcomm PM8010 GPIO support in the PM8010 - Qualcomm SM6115 EGPIO support in the SM6115 - Switch Qualcomm LPASS LPI drivers to use runtime PM for power management - Clean up the Qualcomm Kconfig business a bit to include the necessary drivers for each subarch - Fix output glitch in the Amlogic (meson) A4 pin controller - Move the Airoha driver from the Mediatek directory to its own directory. It is too different from other Mediatek hardware - A slew of fixes to the Airoha AN7581 and AN7583 drivers" * tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits) pinctrl: Export pinctrl_get_group_selector() pinctrl: Match DT helper types pinctrl: qcom: Register functions before enabling pinctrl pinctrl: meson: amlogic-a4: use nolock get range pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller pinctrl: qcom: Remove unused macro definitions pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA pinctrl: tegra238: add missing AON pin groups dt-bindings: pinctrl: tegra238: add missing AON pin groups pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function pinctrl: airoha: an7583: fix phy1_led1 pin function pinctrl: airoha: an7583: add missed gpio22 pin group pinctrl: airoha: an7583: fix gpio21 pin group pinctrl: airoha: fix pwm pin function for an7581 and an7583 pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7583: fix misprint in gpio19 pinconf pinctrl: airoha: an7581: fix misprint in gpio19 pinconf ...
2026-06-15pinctrl: Export pinctrl_get_group_selector()Linus Walleij
The recently added UltraRISC DP1000 is using this symbol, and in a reasonable way as well, so export it. Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Closes: Link: https://lore.kernel.org/linux-gpio/20260613164847.GA3152104@ax162/ Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202606130210.ytVPxHlm-lkp@intel.com/ Fixes: cb7037924836 ("pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver") Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-13pinctrl: Match DT helper typesRob Herring (Arm)
The affected pinctrl drivers either check for the presence of a standard property or read a property documented with an 8-bit cell encoding. Using boolean or u32 helpers for those cases disagrees with the binding. Use a presence helper for "gpio-ranges" and read "microchip,spi-present-mask" with the u8 helper documented by the binding. Assisted-by: Codex:gpt-5-5 Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: qcom: Register functions before enabling pinctrlAlexandre MINETTE
pinctrl consumers can request states while the pinctrl core enables the controller. On Qualcomm pinctrl drivers this can happen before the SoC function list has been registered, which leaves the function table incomplete during state lookup. On APQ8064 this can fail while claiming pinctrl hogs: apq8064-pinctrl 800000.pinctrl: invalid function ps_hold in map table apq8064-pinctrl 800000.pinctrl: error claiming hogs: -22 apq8064-pinctrl 800000.pinctrl: could not claim hogs: -22 Register Qualcomm pinctrl with devm_pinctrl_register_and_init(), add the SoC pin functions, and only then enable the pinctrl device. Signed-off-by: Alexandre MINETTE <contact@alex-min.fr> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: meson: amlogic-a4: use nolock get rangeXianwei Zhao
Use pinctrl_find_gpio_range_from_pin_nolock() instead of pinctrl_find_gpio_range_from_pin() when configuring a pin or setting a GPIO value. This avoids taking the lock and allows the code to be safely called from interrupt context. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driverJia Wang
Add support for the pin controller on the UltraRISC DP1000 SoC. The controller provides mux selection for pins in ports A, B, C, D, and LPC. Ports A-D default to GPIO and support peripheral muxing. LPC pins can be switched to eSPI, but are not available as GPIOs. Basic pin configuration controls such as drive strength, pull-up, and pull-down are also supported. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: qcom: Remove unused macro definitionsNavya Malempati
The macros QUP_I3C and UFS_RESET are defined in some platforms and yet not used. Remove these macros as they are unnecessary. Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRAGeert Uytterhoeven
The NVIDIA Tegra264 MAIN, AON, and UPHY pin controllers are only present on NVIDIA Tegra264 SoCs. Hence add a dependency on ARCH_TEGRA, to prevent asking the user about this driver when configuring a kernel without NVIDIA Tegra SoC support. Fixes: c98506206912dd0d ("pinctrl: tegra: Add Tegra264 pinmux driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRAGeert Uytterhoeven
The NVIDIA Tegra238 MAIN and AON pin controllers are only present on NVIDIA Tegra238 SoCs. Hence add a dependency on ARCH_TEGRA, to prevent asking the user about this driver when configuring a kernel without NVIDIA Tegra SoC support. Fixes: 25cac7292d49f4fc ("pinctrl: tegra: Add Tegra238 pinmux driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: tegra238: add missing AON pin groupsPrathamesh Shete
Add 24 pin groups on ports EE, FF, GG and HH to the AON pin controller group table (tegra238_aon_groups[]). Their pin arrays, drive-group macros and pin descriptors were already defined, but the matching PINGROUP() entries were not present, so these pins could not be muxed or configured through the AON pin controller. The pin arrays were not referenced, so the build emitted -Wunused-const-variable warnings, and commit 119de2c33d96 ("pinctrl: tegra238: remove unused entries") removed three of them. Restore those arrays and add the full set of PINGROUP() entries to make the pins usable. Fixes: 25cac7292d49 ("pinctrl: tegra: Add Tegra238 pinmux driver") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin functionMikhail Kshevetskiy
pcm_spi_int, pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4 pin groups are not defined, so pcm_spi function can't be applied to these groups. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: fix phy1_led1 pin functionMikhail Kshevetskiy
phy1_led1 pin function wrongly refers to gpio1 instead of gpio11. Fix it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: add missed gpio22 pin groupMikhail Kshevetskiy
gpio22 pin group is missed, fix it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: fix gpio21 pin groupMikhail Kshevetskiy
gpio21 pin group refers to gpio22 pin, this is wrong. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: fix pwm pin function for an7581 and an7583Mikhail Kshevetskiy
AN7581 have 47 valid GPIOs only (gpio0-gpio46), so gpio47 is a fiction. AN7583 have 49 valid GPIOs (gpio0-gpio48), so gpio48 is missed To fix an issue * create AN7583 specific pwm pin function, * remove gpio47 from AN7581 pwm pin function. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin functionMikhail Kshevetskiy
phy4_led1 pin function maps led incorrectly. It uses the same map as phy3_led1. PHY{X} should map to LAN{N}_PHY_LED_MAP(X-1). Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin functionMikhail Kshevetskiy
phy4_led1 pin function maps led incorrectly. It uses the same map as phy3_led1. PHY{X} should map to LAN{N}_PHY_LED_MAP(X-1). Fixes: 579839c9548c ("pinctrl: airoha: convert PHY LED GPIO to macro") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: fix misprint in gpio19 pinconfMikhail Kshevetskiy
Pin 21 (gpio19) duplicate pinconf settings of pin 20. Fix it using a proper bit number in the configuration register. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7581: fix misprint in gpio19 pinconfMikhail Kshevetskiy
Pin 32 (gpio19) duplicate pinconf settings of pin 31. Fix it using a proper bit number in the configuration register. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7583: add missed gpio32 pin groupMikhail Kshevetskiy
gpio32 pin group is missed for an7583 SoC. This patch add it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: airoha: an7581: add missed gpio32 pin groupMikhail Kshevetskiy
gpio32 pin group is missed for an7581 SoC. This patch add it. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-11pinctrl: sunxi: a523: Remove unneeded IRQ remuxing flagAndre Przywara
The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when that line is muxed for IRQ triggering (muxval 6), but only if it's explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this behaviour, so we added a optional workaround, triggered by a quirk bit, which triggers remuxing the pin when it's configured for IRQ, while we need to read its value. For some reasons this quirk flag was copied over to newer SoCs, even though they don't show this behaviour, and the GPIO data register reflects the true GPIO state even with a pin muxed to IRQ trigger. Remove the unneeded quirk from the A523 family, where it's definitely not needed (confirmed by experiments), and where it actually breaks, because the workaround is not compatible with the newer generation pinctrl IP used in that chip. Together with a DT change this fixes GPIO IRQ operation on the A523 family of SoCs, as for instance used for the SD card detection. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports") Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-12 04:51:02 +0000