diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-06-16 11:44:45 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-06-30 11:55:37 +0200 |
| commit | 2bbc0f34ef0c056a98f0235fcd8b611e90de5592 (patch) | |
| tree | 4a17585cef1389af82b16a9b4d8600a813f08e30 | |
| parent | 182b03cbe80fea16c8a2f6faaf890e0d8ee0ba46 (diff) | |
| download | linux-stable-2bbc0f34ef0c056a98f0235fcd8b611e90de5592.tar.gz linux-stable-2bbc0f34ef0c056a98f0235fcd8b611e90de5592.zip | |
clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
Add module clock and reset definitions for the USB2.0 interfaces on the
RZ/G3L (r9a08g046) SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260616104459.410743-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a08g046-cpg.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c index edc83a4104b2..4488bd1988e8 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -416,6 +416,16 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = { MSTOP(BUS_MCPU1, BIT(13))), DEF_MOD("ssi3_pclk_sfr", R9A08G046_SSI3_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 7, MSTOP(BUS_MCPU1, BIT(13))), + DEF_MOD("usb_u2h0_hclk", R9A08G046_USB_U2H0_HCLK, R9A08G046_CLK_P1, 0x578, 0, + MSTOP(BUS_PERI_COM, BIT(5))), + DEF_MOD("usb_u2h1_hclk", R9A08G046_USB_U2H1_HCLK, R9A08G046_CLK_P1, 0x578, 1, + MSTOP(BUS_PERI_COM, BIT(7))), + DEF_MOD("usb_u2p0_exr_cpuclk", R9A08G046_USB_U2P0_EXR_CPUCLK, R9A08G046_CLK_P1, 0x578, 2, + MSTOP(BUS_PERI_COM, BIT(6))), + DEF_MOD("usb_pclk", R9A08G046_USB_PCLK, R9A08G046_CLK_P1, 0x578, 3, + MSTOP(BUS_PERI_COM, BIT(4))), + DEF_MOD("usb_u2p1_exr_cpuclk", R9A08G046_USB_U2P1_EXR_CPUCLK, R9A08G046_CLK_P1, 0x578, 4, + MSTOP(BUS_PERI_COM, BIT(13))), DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))), DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1, @@ -531,6 +541,11 @@ static const struct rzg2l_reset r9a08g046_resets[] = { DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2), DEF_RST(R9A08G046_SSI3_RST_M2_REG, 0x870, 3), + DEF_RST(R9A08G046_USB_U2H0_HRESETN, 0x878, 0), + DEF_RST(R9A08G046_USB_U2H1_HRESETN, 0x878, 1), + DEF_RST(R9A08G046_USB_U2P0_EXL_SYSRST, 0x878, 2), + DEF_RST(R9A08G046_USB_PRESETN, 0x878, 3), + DEF_RST(R9A08G046_USB_U2P1_EXL_SYSRST, 0x878, 4), DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0), |