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| author | Oscar Mateo <oscar.mateo@intel.com> | 2017-08-23 12:56:31 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-23 13:31:18 -0700 |
| commit | 2cbecff4122cedff329e3efa32c7f2266125c4a1 (patch) | |
| tree | 6eaa81bc84b71c4df643006fcc7c79590385888c | |
| parent | 66df1014efbadbdd2a550c6c67a815db9b4d05bd (diff) | |
| download | linux-stable-2cbecff4122cedff329e3efa32c7f2266125c4a1.tar.gz linux-stable-2cbecff4122cedff329e3efa32c7f2266125c4a1.zip | |
drm/i915/cnl: WaPushConstantDereferenceHoldDisable
CS sometimes hangs on 3D Push Constant dispatches with the new
deref enhancement logic in CNL.
v2: Improve the commit message (Rodrigo)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1503518191-19116-1-git-send-email-oscar.mateo@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_engine_cs.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d4ecb1905ad8..d9b0249fe5a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8055,6 +8055,7 @@ enum { #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) #define DOP_CLOCK_GATING_DISABLE (1<<0) +#define PUSH_CONSTANT_DEREF_DISABLE (1<<8) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index d23f18874309..d7e1ccf778a2 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1083,6 +1083,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); + /* WaPushConstantDereferenceHoldDisable:cnl */ + WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); + /* WaEnablePreemptionGranularityControlByUMD:cnl */ ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret) |