diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-20 12:09:12 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:23:00 +0100 |
| commit | 2f9f69188e5d1061bab9595edea8e89c7eff75ee (patch) | |
| tree | b40067b8ebadc53e7ae21ca4d8193ebcd31bfa99 | |
| parent | c7259ba78e36967ca124c8fe3b5d2300c814a02a (diff) | |
| download | linux-stable-2f9f69188e5d1061bab9595edea8e89c7eff75ee.tar.gz linux-stable-2f9f69188e5d1061bab9595edea8e89c7eff75ee.zip | |
arm64: dts: renesas: r8a779g0: Restore sort order
Numerical by unit address, but grouped by type.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 104f740d20d3..550e7dabd1da 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2171,6 +2171,24 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x7000>; @@ -2193,6 +2211,28 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779g0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2453,46 +2493,6 @@ }; }; - fcpvx0: fcp@fedb0000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb0000 0 0x200>; - clocks = <&cpg CPG_MOD 1100>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1100>; - iommus = <&ipmmu_vi1 24>; - }; - - fcpvx1: fcp@fedb8000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb8000 0 0x200>; - clocks = <&cpg CPG_MOD 1101>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1101>; - iommus = <&ipmmu_vi1 25>; - }; - - vspx0: vsp@fedd0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd0000 0 0x8000>; - interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1028>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1028>; - - renesas,fcp = <&fcpvx0>; - }; - - vspx1: vsp@fedd8000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd8000 0 0x8000>; - interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1029>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1029>; - - renesas,fcp = <&fcpvx1>; - }; - prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; |