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| author | Stefano Radaelli <stefano.r@variscite.com> | 2025-12-05 19:22:55 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2025-12-30 10:57:07 +0800 |
| commit | 3860538ff7ee027f152d83084a036a84e2cb220b (patch) | |
| tree | 7a43ebe4e4cbebf98ebca9d425283258b57d5426 | |
| parent | 8071668e66e523f36ea57b22f00a73ae63afc5f7 (diff) | |
| download | linux-stable-3860538ff7ee027f152d83084a036a84e2cb220b.tar.gz linux-stable-3860538ff7ee027f152d83084a036a84e2cb220b.zip | |
arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controller
The Symphony carrier board exposes a capacitive touch interface through an
FFC/FPC connector. This interface is wired to an FT5x06 touch controller
on the I2C bus when using Variscite’s 7-inch capacitive touch display.
This patch adds the FT5x06 device node to describe the actual hardware
connection and enables touch functionality on the Symphony board
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 00bdd3b91fdc..39bfbd0428a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -208,6 +208,21 @@ sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + /* DS1337 RTC module */ rtc@68 { compatible = "dallas,ds1337"; @@ -272,6 +287,12 @@ }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e |