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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-07-30 13:24:35 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:43:27 +0200 |
| commit | 45afa9eacb59b258d2e53c7f63430ea1e8344803 (patch) | |
| tree | 0845f7a0832c6014561e2de600ede39529d9fd92 | |
| parent | ab39547f739236e7f16b8b0a51fdca95cc9cadd3 (diff) | |
| download | linux-stable-45afa9eacb59b258d2e53c7f63430ea1e8344803.tar.gz linux-stable-45afa9eacb59b258d2e53c7f63430ea1e8344803.zip | |
arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes
The RZ/V2L SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.
Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0aace8427be3..01f59914dd09 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1051,8 +1051,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; |