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authorKhristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>2026-05-14 10:26:39 +0200
committerFrank Li <Frank.Li@nxp.com>2026-06-05 13:17:46 -0400
commit7ca25f0fa0a8421bdb4c7fc9125a6fe58040ca31 (patch)
tree3b692ce3523e9d014e6a941f360c7f66119a9228
parent65c16cd0def939e86552f1b22ffdbd63b69eebe4 (diff)
downloadlinux-stable-7ca25f0fa0a8421bdb4c7fc9125a6fe58040ca31.tar.gz
linux-stable-7ca25f0fa0a8421bdb4c7fc9125a6fe58040ca31.zip
arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3
Add ADC0 and ADC1 for S32G2 and S32G3 SoCs. Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
-rw-r--r--arch/arm64/boot/dts/freescale/s32g2.dtsi20
-rw-r--r--arch/arm64/boot/dts/freescale/s32g3.dtsi20
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index f508b776b4dd..a1f33197b4b0 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -563,6 +563,16 @@
status = "disabled";
};
+ adc0: adc@401f8000 {
+ compatible = "nxp,s32g2-sar-adc";
+ reg = <0x401f8000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma0 0 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -735,6 +745,16 @@
status = "disabled";
};
+ adc1: adc@402e8000 {
+ compatible = "nxp,s32g2-sar-adc";
+ reg = <0x402e8000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma1 1 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index efe5398e1240..42646b2d16b0 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -626,6 +626,16 @@
status = "disabled";
};
+ adc0: adc@401f8000 {
+ compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
+ reg = <0x401f8000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma0 0 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -810,6 +820,16 @@
status = "disabled";
};
+ adc1: adc@402e8000 {
+ compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
+ reg = <0x402e8000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma1 1 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";