diff options
| author | Luo Jie <quic_luoj@quicinc.com> | 2025-01-03 15:31:38 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-01-06 17:44:06 -0600 |
| commit | 050b312654523aac9495eae3cf7bfa868fd981ce (patch) | |
| tree | 88d4eccee50db3c18effa177c9b3ea3bdcf78993 | |
| parent | 758aa2d7e3c0acfe9c952a1cbe6416ec6130c2a1 (diff) | |
| download | linux-050b312654523aac9495eae3cf7bfa868fd981ce.tar.gz linux-050b312654523aac9495eae3cf7bfa868fd981ce.zip | |
arm64: dts: qcom: ipq9574: Update xo_board_clk to use fixed factor clock
xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock
48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog
block routing channel.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index bb1ff79360d3..ae12f069f26f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -175,8 +175,13 @@ clock-mult = <1>; }; +/* + * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index c543c3492e93..3e93484e7e32 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -32,7 +32,8 @@ }; xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; }; |