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authorRichard Zhu <hongxing.zhu@nxp.com>2025-10-15 11:04:22 +0800
committerShawn Guo <shawnguo@kernel.org>2025-11-12 09:51:28 +0800
commit053ee55576cec9a94a16680a266f242df1872eb9 (patch)
tree853a291cf5415c7ad48a8dff337fe5cfeb2d9fe6
parent45b68efd9bb52d18075f9440dddb3705b72d5810 (diff)
downloadlinux-053ee55576cec9a94a16680a266f242df1872eb9.tar.gz
linux-053ee55576cec9a94a16680a266f242df1872eb9.zip
arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8mq-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-evk.dts2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index a88bc9034663..852992b915a3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -375,6 +375,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
vph-supply = <&vgen5_reg>;
+ supports-clkreq;
status = "okay";
};
@@ -398,6 +399,7 @@
<&clk IMX8MQ_CLK_PCIE2_AUX>;
vpcie-supply = <&reg_pcie1>;
vph-supply = <&vgen5_reg>;
+ supports-clkreq;
status = "okay";
};