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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2026-07-30 10:42:29 +0800
committerTony Luck <tony.luck@intel.com>2026-07-30 11:29:24 -0700
commit141556543c9917d7c3d527f7eca6e288ec6bb58b (patch)
tree7b34a228d927adec6b2172fbafb8208408b17100
parent36a6518e746dcd2e30391c61ce6a8c4bcafd7bb7 (diff)
downloadlinux-141556543c9917d7c3d527f7eca6e288ec6bb58b.tar.gz
linux-141556543c9917d7c3d527f7eca6e288ec6bb58b.zip
EDAC/ie31200: Decouple DIMM width decoding from enum order
The current method to get DIMM width relied on DEV_* enum ordering via a linear offset (+ DEV_X8), tightly coupling hardware encoding to enum layout. Replace it with explicit decoding to remove this dependency, as the enum is expected to grow with additional device widths. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-2-qiuxu.zhuo@intel.com
-rw-r--r--drivers/edac/ie31200_edac.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index e3bd6436669b..bfd54012ae47 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -416,7 +416,23 @@ static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm,
{
dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity;
dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1;
- dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8;
+
+ switch (field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode)) {
+ case 0:
+ dd->dtype = DEV_X8;
+ break;
+ case 1:
+ dd->dtype = DEV_X16;
+ break;
+ case 2:
+ dd->dtype = DEV_X32;
+ break;
+ case 3:
+ dd->dtype = DEV_X64;
+ break;
+ default:
+ dd->dtype = DEV_UNKNOWN;
+ }
}
static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window,