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| author | Matthew Gerlach <matthew.gerlach@altera.com> | 2025-06-25 08:14:42 -0700 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2025-07-12 07:24:48 -0500 |
| commit | 203b862057d08fbabcd4e475707751c0f2a9258b (patch) | |
| tree | b7cc1db5a2bb7fc907eba839029fcd4e4a3ec827 | |
| parent | 1dfe3ca86a9c43e2e49be6c4235b3170c5059e46 (diff) | |
| download | linux-203b862057d08fbabcd4e475707751c0f2a9258b.tar.gz linux-203b862057d08fbabcd4e475707751c0f2a9258b.zip | |
arm64: dts: altera: socfpga_stratix10: update internal oscillators
Add the clock-frequency property to the cb_intosc_ls_clk and
cb_intosc_hs_div2_clk device tree nodes.
The f2s_free_clk is implemented by custom logic in the FPGA; so it
should be disabled in the dtsi by default and enabled by a
dts for a specific FPGA design on a specific board.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index f0f659139f22..effd242f6bf7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -130,16 +130,19 @@ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <150000000>; }; cb_intosc_ls_clk: cb-intosc-ls-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <300000000>; }; f2s_free_clk: f2s-free-clk { #clock-cells = <0>; compatible = "fixed-clock"; + status = "disabled"; }; osc1: osc1 { |