diff options
| author | Dillon Varone <dillon.varone@amd.com> | 2022-04-13 17:54:19 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:45:00 -0400 |
| commit | 2267a195e28cc438cb45936c4562f958502d4038 (patch) | |
| tree | 78783248f7fd34ff31ff3b34f03dbd12651f3b5c | |
| parent | 2cfe34e18970d26bff73c63f16c76dae22138d19 (diff) | |
| download | linux-2267a195e28cc438cb45936c4562f958502d4038.tar.gz linux-2267a195e28cc438cb45936c4562f958502d4038.zip | |
drm/amd/display: Disable DTB Ref Clock Switching in dcn32
[How & Why]
To be enabled once PMFW supports it.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 774de29fa532..f147c65137c6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct( if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ + if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { + clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; + } + if (clk_mgr->base.boot_snapshot.dprefclk != 0) { //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; |