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authorFrank Li <Frank.Li@nxp.com>2025-10-28 16:30:42 -0400
committerShawn Guo <shawnguo@kernel.org>2025-11-16 17:45:52 +0800
commit2984af793281bc269fc8de3a204400fbfdbe42a7 (patch)
tree9a02666efcb105dcc231b625333f3323234d4438
parent09b33db32e1df762feb64725a11d3eb9eab0b25f (diff)
downloadlinux-2984af793281bc269fc8de3a204400fbfdbe42a7.tar.gz
linux-2984af793281bc269fc8de3a204400fbfdbe42a7.zip
arm64: dts: imx8qm-mek: add state_100mhz and state_200mhz for usdhc
default, state_100mhz and state_200mhz use the same settings. But current driver use these to indicate if sd3.0 support. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-mek.dts18
1 files changed, 15 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 09b01e56ea00..0371de764e24 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -811,8 +811,10 @@
};
&usdhc1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
@@ -821,8 +823,10 @@
};
&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
@@ -1239,4 +1243,12 @@
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
+ >;
+ };
};