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authorJoe Sandom <jsandom@axon.com>2026-04-20 10:13:13 +0100
committerBjorn Andersson <andersson@kernel.org>2026-07-02 14:31:22 -0500
commit347318325974e888dc18d9fd15dcc48f671886c9 (patch)
treeac55d479a7bba997d23577de905abfaff2ef1d7b
parent4c53f51b442ae8cc4545fc5ec349ce6ed7afb4cf (diff)
downloadlinux-347318325974e888dc18d9fd15dcc48f671886c9.tar.gz
linux-347318325974e888dc18d9fd15dcc48f671886c9.zip
arm64: dts: qcom: sm8550: add PCIe MHI register regions
Add the MHI register regions to the pcie0 and pcie1 controller nodes to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2) via debugfs. The PCIe host driver uses this region to read the link_transition_count from the MHI registers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Joe Sandom <jsandom@axon.com> Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-1-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550.dtsi20
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 396201905ef2..1f2cafb1c380 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2321,8 +2321,14 @@
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
@@ -2495,8 +2501,14 @@
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
- <0x0 0x40100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,