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| author | Joshua Milas <josh.milas@gmail.com> | 2026-06-15 08:03:23 -0400 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@gmail.com> | 2026-08-04 18:04:16 +0800 |
| commit | 418bd91075ccee25828db79390848da1ab3ef0a7 (patch) | |
| tree | 580f4569b81b748a7903b17399ef69b671c9c86b | |
| parent | 5011466bade64483bb52bc4a926719d6794e6dab (diff) | |
| download | linux-418bd91075ccee25828db79390848da1ab3ef0a7.tar.gz linux-418bd91075ccee25828db79390848da1ab3ef0a7.zip | |
riscv64: dts: sophgo: add SG2000 dtsi
Adds sg2000.dtsi on the RISCV side.
Signed-off-by: Joshua Milas <josh.milas@gmail.com>
Tested-by: Gui-Dong Han <hanguidong02@gmail.com>
Reviewed-by: Gui-Dong Han <hanguidong02@gmail.com>
Link: https://patch.msgid.link/20260615120324.1527881-3-josh.milas@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..38462769574f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/pinctrl-sg2000.h> +#include "cv180x-cpus.dtsi" +#include "cv180x.dtsi" +#include "cv181x.dtsi" + +/ { + compatible = "sophgo,sg2000"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + soc { + interrupt-parent = <&plic>; + dma-noncoherent; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + + clk: clock-controller@3002000 { + compatible = "sophgo,sg2000-clk"; + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,sg2000-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,sg2000-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; |