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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2022-02-10 10:48:58 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-02-15 17:06:37 +0100 |
| commit | 478b09fa2c00cbc40d25bc061befdf11f04a27ad (patch) | |
| tree | 1e845dec147737d9412e384f72f9dc2b172a2dfd | |
| parent | 5d2ed511b4a220332eb17725757dda433e9d35c4 (diff) | |
| download | linux-478b09fa2c00cbc40d25bc061befdf11f04a27ad.tar.gz linux-478b09fa2c00cbc40d25bc061befdf11f04a27ad.zip | |
dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
Make system controller a reset provider for all the peripherals in the
MT7621 SoC adding '#reset-cells' property.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: <include/dt-bindings/reset/mt7621-reset.h>. + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", |