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authorSimon Glass <sjg@chromium.org>2026-08-03 08:10:23 -0600
committerLinus Walleij <linusw@kernel.org>2026-08-07 00:11:05 +0200
commit5b695c191cc85f0fd62eec885b55d01468dc9f2c (patch)
treee40ac3b2bd609aa49502eb467402063cff915c4b
parent27e5b8efc25b9238865288b7091ae6915c2f7c14 (diff)
downloadlinux-5b695c191cc85f0fd62eec885b55d01468dc9f2c.tar.gz
linux-5b695c191cc85f0fd62eec885b55d01468dc9f2c.zip
pinctrl: rockchip: Reset the pin count when recalculating SoC data
rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The iomux and drive offsets are recalculated idempotently, since a rerun anchors at the values calculated before, but the total pin count only accumulates: each run adds every bank's pins again. When the probe is deferred and runs a second time, nr_pins doubles and every bank's pin_base shifts, so later pin lookups resolve to the wrong bank and the wrong registers. Reset the pin count at the start of the calculation, so that a rerun produces the same values. This is verified on a Luckfox Pico Mini B (RV1103, with the pending RV1106 series applied) by forcing the probe to defer once: without this patch the second probe calculates nr_pins=304 instead of 152 and no GPIO bank comes up; with it the recalculation matches the first run and all banks work. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=4 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index e90e13c5d7f2..dbbbfdc73848 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -4437,6 +4437,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
pmu_offs = ctrl->pmu_mux_offset;
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
+
+ /*
+ * This function mutates the static per-SoC data. Most of it is
+ * idempotent: recalculated iomux and drv offsets anchor at the
+ * values calculated by a previous run. The pin count is not, so
+ * reset it here; otherwise it accumulates when the probe runs
+ * again after a probe deferral, shifting every bank's pin_base.
+ */
+ ctrl->nr_pins = 0;
+
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;