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| author | Sherry Sun <sherry.sun@nxp.com> | 2026-04-22 17:35:48 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-05 13:17:10 -0400 |
| commit | 5e5bcc5a80a2d802e7d9d1523682b9e054cbbfcf (patch) | |
| tree | 3512d4f14737896954f94826afad18942045aec9 | |
| parent | 2f42bbebb7bef302b190f8965b7a675268567aa1 (diff) | |
| download | linux-5e5bcc5a80a2d802e7d9d1523682b9e054cbbfcf.tar.gz linux-5e5bcc5a80a2d802e7d9d1523682b9e054cbbfcf.zip | |
arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 |
5 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 469de8b536b5..009990b2e559 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -78,6 +78,17 @@ hsio_subsys: bus@5f000000 { power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcieb_ep: pcie-ep@5f010000 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 441e00903029..78e8d41e6791 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -675,6 +675,7 @@ phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; @@ -689,6 +690,10 @@ status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 011a89d85961..f706c86137c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -810,6 +810,7 @@ phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pciea>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pciea>; vpcie3v3aux-supply = <®_pciea>; @@ -817,15 +818,24 @@ status = "okay"; }; +&pciea_port0 { + reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; +}; + &pcieb { phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; +}; + &qm_pwm_lvds0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_lvds0>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index f2c94cdb682b..2e4fbfe0ca16 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -41,6 +41,17 @@ power-domains = <&pd IMX_SC_R_PCIE_A>; fsl,max-link-speed = <3>; status = "disabled"; + + pciea_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pciea_ep: pcie-ep@5f000000 { @@ -91,6 +102,17 @@ power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; sata: sata@5f020000 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index c07138055229..2af32eca612a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -730,6 +730,7 @@ phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; @@ -745,6 +746,10 @@ status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &scu_key { status = "okay"; }; |
