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| author | Luca Weiss <luca.weiss@fairphone.com> | 2026-04-30 09:10:44 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-05-09 21:35:18 -0500 |
| commit | 630398127110753474576cbc0cd4ad102b18005e (patch) | |
| tree | a5dc1db1107bf261a25398de3e69b0e7ff7c45e4 | |
| parent | bde860892c92a43624a7bcf932a1d375b1ad43eb (diff) | |
| download | linux-630398127110753474576cbc0cd4ad102b18005e.tar.gz linux-630398127110753474576cbc0cd4ad102b18005e.zip | |
arm64: dts: qcom: sm6350: add LPASS LPI pin controller
Add LPASS LPI pinctrl node required for audio functionality on SM6350.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 034545d2af2d..d6adf68563cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1450,6 +1450,72 @@ }; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x0 0x033c0000 0x0 0x20000>, + <0x0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + i2s1_sleep: i2s1-sleep-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-619.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, |