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| author | Jouni Högander <jouni.hogander@intel.com> | 2025-05-26 15:05:09 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-05-29 08:13:43 +0300 |
| commit | 7acc76a37e5d5743102784be82e6ae6dd784043c (patch) | |
| tree | 4754528dd1d82d13c408c5eb80f12aec6e7fd511 | |
| parent | 6ecb8e586f8339657211e12fcba7f77bae297fdd (diff) | |
| download | linux-7acc76a37e5d5743102784be82e6ae6dd784043c.tar.gz linux-7acc76a37e5d5743102784be82e6ae6dd784043c.zip | |
drm/i915/display: Add PHY_CMN1_CONTROL register definitions
Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.
Bspec: 68962
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-10-jouni.hogander@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 59c22beaf1de..580a43be195e 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -285,6 +285,9 @@ #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control)) #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6) +#define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control)) +#define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1) + /* C20 Registers */ #define PHY_C20_WR_ADDRESS_L 0xC02 #define PHY_C20_WR_ADDRESS_H 0xC03 |