diff options
| author | Ashish Mhetre <amhetre@nvidia.com> | 2026-06-22 06:54:09 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-07-16 23:46:35 +0200 |
| commit | 85220be437fa0cf8515a172848ca71fc298dfde7 (patch) | |
| tree | e031bcacb7d65dca9fc7b8e8c174c1593f13dbad | |
| parent | dc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff) | |
| download | linux-85220be437fa0cf8515a172848ca71fc298dfde7.tar.gz linux-85220be437fa0cf8515a172848ca71fc298dfde7.zip | |
dt-bindings: iommu: Fix interrupt type in example
The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
interrupt documentation, but the binding example describes it as
level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
that it does not propagate the wrong trigger type.
Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; }; |