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| author | Icenowy Zheng <zhengxingda@iscas.ac.cn> | 2026-04-08 00:01:43 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@gmail.com> | 2026-06-03 10:09:38 +0800 |
| commit | 903a9364e40563faf4730dc63ad7446246f494ff (patch) | |
| tree | 49a978e9fcedb112bd5a01b2d166302956705b0c | |
| parent | a7e658907686528fe06a11828b04a3e42df9ef18 (diff) | |
| download | linux-903a9364e40563faf4730dc63ad7446246f494ff.tar.gz linux-903a9364e40563faf4730dc63ad7446246f494ff.zip | |
riscv: dts: sophgo: reduce SG2042 MSI count to 16
The SG2042 MSI controller has one 32-bit doorbell register, and each bit
corresponds to an interrupt. At a glance, it seems that the MSI
controller can support 32 interrupts; however the PCI MSI capability
only supports 16-bit messages, which makes the high 16 interrupts
unusable in such way.
Reduce the MSI count to 16 to prevent producing MSI message values that
cannot fit 16-bit integers.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 3af770549742..7eab0655f150 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -234,7 +234,7 @@ reg-names = "clr", "doorbell"; msi-controller; #msi-cells = <0>; - msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; + msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; }; rpgate: clock-controller@7030010368 { |