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| author | Thierry Reding <treding@nvidia.com> | 2025-10-30 20:31:03 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2025-10-30 20:31:03 +0100 |
| commit | c0ff2845849c73e8f32bb3f35e1f799b47173dc7 (patch) | |
| tree | 602a6f421d6ce2ffc143081f61ab2c7e89aaf828 | |
| parent | ce121914f38aaa59504e20a1a625e5988fc6ead4 (diff) | |
| parent | ccec1069246ad121c1cbb6494d75140d512a9b5b (diff) | |
| download | linux-c0ff2845849c73e8f32bb3f35e1f799b47173dc7.tar.gz linux-c0ff2845849c73e8f32bb3f35e1f799b47173dc7.zip | |
Merge branch 'for-6.19/dt-bindings' into for-6.19/arm64/dt
| -rw-r--r-- | Documentation/devicetree/bindings/arm/tegra.yaml | 5 | ||||
| -rw-r--r-- | include/dt-bindings/power/nvidia,tegra264-bpmp.h | 24 |
2 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 6139407c2cbf..50a31dba7bec 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -189,6 +189,11 @@ properties: - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2894-0050-a08 + - nvidia,p3450-0000 + - const: nvidia,tegra210 + - items: + - const: nvidia,p3541-0000 + - const: nvidia,p3450-0000 - const: nvidia,tegra210 - description: Jetson TX2 Developer Kit items: diff --git a/include/dt-bindings/power/nvidia,tegra264-bpmp.h b/include/dt-bindings/power/nvidia,tegra264-bpmp.h new file mode 100644 index 000000000000..2eef4a2a02b0 --- /dev/null +++ b/include/dt-bindings/power/nvidia,tegra264-bpmp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H +#define DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H + +#define TEGRA264_POWER_DOMAIN_DISP 1 +#define TEGRA264_POWER_DOMAIN_AUD 2 +/* reserved 3:9 */ +#define TEGRA264_POWER_DOMAIN_XUSB_SS 10 +#define TEGRA264_POWER_DOMAIN_XUSB_DEV 11 +#define TEGRA264_POWER_DOMAIN_XUSB_HOST 12 +#define TEGRA264_POWER_DOMAIN_MGBE0 13 +#define TEGRA264_POWER_DOMAIN_MGBE1 14 +#define TEGRA264_POWER_DOMAIN_MGBE2 15 +#define TEGRA264_POWER_DOMAIN_MGBE3 16 +#define TEGRA264_POWER_DOMAIN_VI 17 +#define TEGRA264_POWER_DOMAIN_VIC 18 +#define TEGRA264_POWER_DOMAIN_ISP0 19 +#define TEGRA264_POWER_DOMAIN_ISP1 20 +#define TEGRA264_POWER_DOMAIN_PVA0 21 +#define TEGRA264_POWER_DOMAIN_GPU 22 + +#endif /* DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H */ |