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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 09:46:34 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-03-06 10:01:46 +0800 |
| commit | c812c91bda8d3b4d9ea23c52bf88a20de64f7487 (patch) | |
| tree | b64eed14928481631a9bc043d09c2b6cbdda0b96 | |
| parent | 2c23a919d655700f2b567ced1ed0307bfdede05e (diff) | |
| download | linux-c812c91bda8d3b4d9ea23c52bf88a20de64f7487.tar.gz linux-c812c91bda8d3b4d9ea23c52bf88a20de64f7487.zip | |
ARM: dts: imx6q-prtwd2: configure ethernet reference clock parent
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6q-prtwd2.dts | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts index 349959d38020..54a57a4548e2 100644 --- a/arch/arm/boot/dts/imx6q-prtwd2.dts +++ b/arch/arm/boot/dts/imx6q-prtwd2.dts @@ -22,6 +22,13 @@ reg = <0x80000000 0x20000000>; }; + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -49,13 +56,17 @@ status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>; - clock-names = "ipg", "ahb"; status = "okay"; fixed-link { |