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| author | Beleswar Padhi <b-padhi@ti.com> | 2025-09-08 19:58:10 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2025-09-12 09:45:30 +0530 |
| commit | e85524649959c2fa2477b66a450471df6e1fb725 (patch) | |
| tree | d83353c9a81520641e2062bd897953cefcc59101 | |
| parent | 6104984a7d1d8c17c724e799501a1be2a2a35a52 (diff) | |
| download | linux-e85524649959c2fa2477b66a450471df6e1fb725.tar.gz linux-e85524649959c2fa2477b66a450471df6e1fb725.zip | |
arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware
Currently, only R5F remote processors are enabled for k3-am642-sr SoMs,
whereas the M4F in MCU domain is disabled. Enable the M4F remote
processor at board level by reserving memory carveouts and assigning
mailboxes.
While at it, reserve the MAIN domain timers that are used by R5F remote
processors for ticks to avoid rproc crashes. This config aligns with
other AM64 boards and can be refactored out later.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-19-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index 35294a5c46d5..38feda717d7a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ }; }; +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ status = "okay"; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names = "default"; |