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| author | Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> | 2026-06-03 12:22:17 +0530 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2026-06-03 13:47:03 -0700 |
| commit | f22dbf90f011fa1ae0fe02841fb2676f87633783 (patch) | |
| tree | f7d21a044ef72b1d6bd4a75a726917574ef161ea | |
| parent | 4b1ae138b0e103d753773956a84eebc2edbf62c4 (diff) | |
| download | linux-f22dbf90f011fa1ae0fe02841fb2676f87633783.tar.gz linux-f22dbf90f011fa1ae0fe02841fb2676f87633783.zip | |
drm/xe: explicit TLB flush for context based tlb invalidation
In LR preempt-fence mode, on devices with context based
TLB Invalidation, rebind operations for VMAs require
an explicit invalidation request.
Request explicit TLB Invalidation in notifier path
and in PT path.
Userptr VMAs are excluded in PT path since the notifier path
already submits invalidation, preventing duplicate
requests for the same rebind window.
v2: Remove explicit TLB Invalidation in notifier path as
PT path is sufficient.
Refactor of above to remove exclusion of userptr VMAs n
PT path.- Thomas
v3: Knit-Remove unrelated change.-Thomas
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Reviewed-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patch.msgid.link/20260603065217.3131066-4-tilak.tirumalesh.tangudu@intel.com
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pt.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index 2669ff5ee747..15ce77ce7793 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -2010,6 +2010,9 @@ static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile, * automatically when the context is re-enabled by the rebind worker, * or in fault mode it was invalidated on PTE zapping. * + * If rebind, we have to invalidate TLB on context based TLB invalidation + * LR vms, as they cannot be relied on context re-enable. + * * If !rebind, and scratch enabled VMs, there is a chance the scratch * PTE is already cached in the TLB so it needs to be invalidated. * On !LR VMs this is done in the ring ops preceding a batch, but on @@ -2019,6 +2022,9 @@ static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile, if ((!pt_op->rebind && xe_vm_has_scratch(vm) && xe_vm_in_lr_mode(vm))) pt_update_ops->needs_invalidation = true; + else if (pt_op->rebind && xe_vm_in_preempt_fence_mode(vm) && + vm->xe->info.has_ctx_tlb_inval) + pt_update_ops->needs_invalidation = true; else if (pt_op->rebind && !xe_vm_in_lr_mode(vm)) /* We bump also if batch_invalidate_tlb is true */ vm->tlb_flush_seqno++; |