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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-26 11:06:37 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-04-27 11:40:04 +0200 |
| commit | f232745679fe1b8dfc545d2bbb4b5cd1c50b3237 (patch) | |
| tree | 084acbe9b2f6fefe3a5e52f333657a1f4dee0e18 | |
| parent | 78db1faa6b681da20ec167268b28778ebb0f98b7 (diff) | |
| download | linux-f232745679fe1b8dfc545d2bbb4b5cd1c50b3237.tar.gz linux-f232745679fe1b8dfc545d2bbb4b5cd1c50b3237.zip | |
clk: renesas: r8a08g046: Add support for PLL6
Add support for the PLL6 clk by registering it with rzg2l-cpg driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326110648.29389-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a08g046-cpg.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c index 6759957980f2..fed9607af216 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -29,6 +29,9 @@ #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) +/* PLL 1/4/6/7 configuration registers macro. */ +#define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting)) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A08G046_USB_SCLK, @@ -45,6 +48,7 @@ enum clk_ids { CLK_PLL2_DIV2, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL6, /* Module Clocks */ MOD_CLK_BASE, @@ -78,6 +82,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = { /* Internal Core Clocks */ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, G3L_PLL1467_CONF(0x54, 0x58, 0), + 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), |