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| author | Zeng Heng <zengheng4@huawei.com> | 2026-06-03 14:20:25 +0800 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-06-03 12:43:28 +0100 |
| commit | f64328ecf4bf354d1ddf88542dc21a151ce5a2c4 (patch) | |
| tree | 881604baa2a7c806650e8b185251e85ad5045957 | |
| parent | 25996982ebcf8242c9e44589f8dd1ed760df8ac0 (diff) | |
| download | linux-f64328ecf4bf354d1ddf88542dc21a151ce5a2c4.tar.gz linux-f64328ecf4bf354d1ddf88542dc21a151ce5a2c4.zip | |
arm64: kernel: Disable CNP on HiSilicon HIP09
HiSilicon HIP09 implements TLB entry matching behavior that deviates
from the ARM architecture specification when the CNP (Common not Private)
bit is set in TTBRx_ELx.
When TTBRx.CNP=1, TLB entries may be incorrectly shared between CPU
cores, leading to TLB conflicts and stale mappings. This affects
coherency and can result in incorrect translations.
Add the hardware erratum workaround (Hisilicon erratum 162100125) to
disable CNP on affected HIP09 cores.
Co-developed-by: Tong Tiangen <tongtiangen@huawei.com>
Signed-off-by: Tong Tiangen <tongtiangen@huawei.com>
Signed-off-by: Zeng Heng <zengheng4@huawei.com>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/arch/arm64/silicon-errata.rst | 2 | ||||
| -rw-r--r-- | arch/arm64/Kconfig | 16 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 6 |
3 files changed, 22 insertions, 2 deletions
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 046a7fa47063..61c2fd7ef644 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -287,6 +287,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_162100801 | +----------------+-----------------+-----------------+-----------------------------+ +| Hisilicon | Hip09 | #162100125 | HISILICON_ERRATUM_162100125 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f297517a83b9..75638e37883d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1273,6 +1273,22 @@ config HISILICON_ERRATUM_162100801 If unsure, say Y. +config HISILICON_ERRATUM_162100125 + bool "Hisilicon erratum 162100125" + default y + select ARM64_WORKAROUND_DISABLE_CNP + help + On HiSilicon HIP09, TLB entry matching behavior when CNP + (TTBRx.CNP=1) is enabled differs from the ARM architecture + specification. + + TLB entries may be incorrectly shared between CPUs, potentially + causing TLB conflicts and stale mappings. + + Disable CNP support for affected HiSilicon HIP09 cores. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 08eb9d6545d1..310e6f120992 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -613,6 +613,9 @@ static const struct midr_range cnp_erratum_cpus[] = { #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), #endif +#ifdef CONFIG_HISILICON_ERRATUM_162100125 + MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), +#endif {}, }; #endif @@ -812,8 +815,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { #endif #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP { - /* NVIDIA Carmel */ - .desc = "NVIDIA Carmel CNP erratum", + .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", .capability = ARM64_WORKAROUND_DISABLE_CNP, ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), }, |