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| author | Esteban Urrutia <esteuwu@proton.me> | 2026-07-15 02:37:47 -0400 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-08-07 11:53:37 +0530 |
| commit | f8b4493d5e7e19682abcf538a9faad012b5ef69e (patch) | |
| tree | f037d2b14a9d0ad11a14a834c299bf3010484fa8 | |
| parent | bae047e91213a7b8f86b70f0f48f38374a73d5ea (diff) | |
| download | linux-f8b4493d5e7e19682abcf538a9faad012b5ef69e.tar.gz linux-f8b4493d5e7e19682abcf538a9faad012b5ef69e.zip | |
phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets
Some SoCs such as SM8475 write data to registers using this offset,
specifically SW_CTRL2 and MX_CTRL2.
Add pcs_lane1 offset to V5 offsets to support this.
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Fixes: 0fd0b31965b0 ("phy: qualcomm: qmp-pcie: add support for SAR2130P")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-2-48bd91a19abf@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 27034bb62d0d..5bebc6baadfe 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4092,6 +4092,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { .pcs_misc = 0x0600, .tx = 0x0e00, .rx = 0x1000, + .pcs_lane1 = 0x1400, .tx2 = 0x1600, .rx2 = 0x1800, }; |