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| author | Guodong Xu <guodong@riscstar.com> | 2026-08-07 19:24:33 -0600 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-08-07 19:24:33 -0600 |
| commit | fdef048705daa3d4ed1fa212ee071bcbdac02d80 (patch) | |
| tree | 07bf3d504ee9f52ce1882aa3c10498f61fb0d8f1 | |
| parent | 0c5a9ab5192b8cc15fa7b32a1f747c70aaee51b0 (diff) | |
| download | linux-fdef048705daa3d4ed1fa212ee071bcbdac02d80.tar.gz linux-fdef048705daa3d4ed1fa212ee071bcbdac02d80.zip | |
riscv: cpufeature: Clarify ISA spec version for canonical order
Specify that chapter 27 refers to version 20191213 of the RISC-V ISA
Unprivileged Architecture. The chapter numbering differs across
specification versions - for example, in version 20250508, the ISA
Extension Naming Conventions is chapter 36, not chapter 27.
Historical versions of the RISC-V specification can be found via Link [1].
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://riscv.org/specifications/ratified/ [1]
Fixes: 99e2266f2460 ("RISC-V: clarify ISA string ordering rules in cpu.c")
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://patch.msgid.link/20260125-supm-ext-id-v2-3-1e3b9714c860@riscstar.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
| -rw-r--r-- | arch/riscv/kernel/cpufeature.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ebe4a2593c40..16488b33f238 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -473,7 +473,8 @@ static const unsigned int riscv_c_exts[] = { /* * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. + * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA + * (Document Version 20191213). * * Ordinarily, for in-kernel data structures, this order is unimportant but * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. |