Merge branch 'pci/controller/dwc-intel-gw'

- Enable clock before PHY init for correct ordering (Florian Eckert)

- Add .start_link() callback so the driver works again (Florian Eckert)

- Stop overwriting the ATU base address discovered by
  dw_pcie_get_resources() (Florian Eckert)

- Add DT 'atu' region since this is hardware-specific, and fall back to
  driver default if lacking (Florian Eckert)

* pci/controller/dwc-intel-gw:
  dt-bindings: PCI: intel,lgm-pcie: Add 'atu' resource
  PCI: intel-gw: Fix ATU base address setup and add optional DT 'atu' region
  PCI: intel-gw: Add .start_link() callback
  PCI: intel-gw: Enable clock before PHY init
  PCI: intel-gw: Move interrupt enable to own function
  PCI: intel-gw: Remove unused PCIE_APP_INTX_OFST definition

1 files changed, 7 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
index 54e2890ae631..394bb46b38e6 100644
--- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
@@ -27,16 +27,20 @@ properties:
       - const: snps,dw-pcie
 
   reg:
+    minItems: 3
     items:
       - description: Controller control and status registers.
       - description: PCIe configuration registers.
       - description: Controller application registers.
+      - description: Internal Address Translation Unit (iATU) registers.
 
   reg-names:
+    minItems: 3
     items:
       - const: dbi
       - const: config
       - const: app
+      - const: atu
 
   ranges:
     maxItems: 1
@@ -95,8 +99,9 @@ examples:
       #size-cells = <2>;
       reg = <0xd0e00000 0x1000>,
             <0xd2000000 0x800000>,
-            <0xd0a41000 0x1000>;
-      reg-names = "dbi", "config", "app";
+            <0xd0a41000 0x1000>,
+            <0xd0ec0000 0x1000>;
+      reg-names = "dbi", "config", "app", "atu";
       linux,pci-domain = <0>;
       max-link-speed = <4>;
       bus-range = <0x00 0x08>;