diff options
| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2026-08-07 20:11:30 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2026-08-07 20:11:30 +0200 |
| commit | 02859a576afde166daceffdfb8eefc540fbfff9b (patch) | |
| tree | 7bd0182920b15d8e8c1f5971feeb612c96050e43 /arch | |
| parent | 9341ba27436ecf458cd6e1f33d93109b79143fb6 (diff) | |
| parent | d2aa7b179a711d045cdeb4dfb33428207ae32b4b (diff) | |
| download | linux-02859a576afde166daceffdfb8eefc540fbfff9b.tar.gz linux-02859a576afde166daceffdfb8eefc540fbfff9b.zip | |
Merge branch 'acpi-irqchip'
Merge irqchip changes related to ACPI support that are needed to enable
GICv5 IWB ACPI probe ordering detection on ARM, including the addition
of acpi_device_clear_deps() and RISC-V interrupt controller management
code refactoring to extract generic code from it into the common ACPI
IRQ code (Lorenzo Pieralisi)
* acpi-irqchip:
irqchip/gic-v5: Enable GICv5 IWB ACPI probe ordering detection
ACPI/IORT: Implement ACPI infrastructure to enable GICv5 IWB probe deferral
ACPI: irq: Move RISC-V interrupt controllers autodep to ACPI IRQ code
ACPI: RISC-V: Fix riscv_acpi_add_prt_dep() loop handling
ACPI: RISC-V: Check acpi_get_handle() status in riscv_acpi_add_prt_dep()
ACPI: RISC-V: Fix riscv_acpi_irq_get_dep() loop termination
ACPI: Add acpi_device_clear_deps() helper function
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/include/asm/acpi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 26ab37c171bc..f598520ac903 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -67,6 +67,7 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size); +acpi_handle acpi_get_riscv_gsi_handle(u32 gsi); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) |