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| author | Priya Hosur <Priya.Hosur@amd.com> | 2026-06-04 18:34:18 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-06 09:27:12 -0400 |
| commit | ae60a2b05f813d434591c2d897222ba9cdff173f (patch) | |
| tree | 1f9c54038a7cb8c58076a8df9b64634992f61227 /drivers | |
| parent | 19d408ea197a66d3a20818e759ca216eb9020760 (diff) | |
| download | linux-ae60a2b05f813d434591c2d897222ba9cdff173f.tar.gz linux-ae60a2b05f813d434591c2d897222ba9cdff173f.zip | |
drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queries
Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and
smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with
NumDcfClkLevelsEnabled bounds check. Add matching case in both
get_dpm_level_count functions.
Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels.
No * marker is emitted since SmuMetrics_t has no DcfclkFrequency
field (same firmware limitation as Phoenix).
Without this, pp_dpm_dcefclk reports N/A on Strix Halo.
Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index 98e38cc23d52..7cf522609583 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -734,6 +734,11 @@ static int smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu, return -EINVAL; *freq = clk_table->FclkClocks_Freq[dpm_level]; break; + case SMU_DCEFCLK: + if (dpm_level >= clk_table->NumDcfClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->DcfClocks[dpm_level]; + break; default: return -EINVAL; } @@ -778,6 +783,11 @@ static int smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu, return -EINVAL; *freq = clk_table->FclkClocks_Freq[dpm_level]; break; + case SMU_DCEFCLK: + if (dpm_level >= clk_table->NumDcfClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->DcfClocks[dpm_level]; + break; default: return -EINVAL; } @@ -1141,6 +1151,9 @@ static int smu_v14_0_1_get_dpm_level_count(struct smu_context *smu, case SMU_FCLK: *count = clk_table->NumFclkLevelsEnabled; break; + case SMU_DCEFCLK: + *count = clk_table->NumDcfClkLevelsEnabled; + break; default: break; } @@ -1170,6 +1183,9 @@ static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu, case SMU_FCLK: *count = clk_table->NumFclkLevelsEnabled; break; + case SMU_DCEFCLK: + *count = clk_table->NumDcfClkLevelsEnabled; + break; default: break; } @@ -1236,6 +1252,18 @@ static int smu_v14_0_0_emit_clk_levels(struct smu_context *smu, cur_value == value ? "*" : ""); } break; + case SMU_DCEFCLK: + ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count); + if (ret) + return ret; + + for (i = 0; i < count; i++) { + ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) + return ret; + size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i, value); + } + break; case SMU_GFXCLK: case SMU_SCLK: ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value); |