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authorEkansh Gupta <ekansh.gupta@oss.qualcomm.com>2026-07-29 10:43:48 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-07-31 14:15:53 +0200
commit62373b7879ada744ea4fc6766b2fb55229eac11f (patch)
tree99017ab7713e7918d87e04fd101fbea19d20b4d5 /include/uapi
parent713b54b86aab2ba2e477540f707a7aa6d295d443 (diff)
downloadlinux-62373b7879ada744ea4fc6766b2fb55229eac11f.tar.gz
linux-62373b7879ada744ea4fc6766b2fb55229eac11f.zip
misc: fastrpc: Expand context ID mask for DSP polling mode support
Current FastRPC context uses a 12-bit mask: [ID(8 bits)][PD type(4 bits)] = GENMASK(11, 4) This works for normal calls but fails for DSP polling mode. Polling mode expects a 16-bit layout: [15:8] = context ID (8 bits) [7:5] = reserved [4] = async mode bit [3:0] = PD type (4 bits) If async bit (bit 4) is set, DSP disables polling. With current mask, odd IDs can set this bit, causing DSP to skip poll updates. Update FASTRPC_CTXID_MASK to GENMASK(15, 8) so IDs occupy upper byte and lower byte is left for DSP flags and PD type. Reserved bits remain unused. This change is compatible with polling mode and does not break non-polling behavior. Bit layout: [15:8] = CCCCCCCC (context ID) [7:5] = xxx (reserved) [4] = A (async mode) [3:0] = PPPP (PD type) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://patch.msgid.link/20260729094352.111065-7-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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