diff options
| author | Chen-Yu Tsai <wenst@chromium.org> | 2026-07-28 17:17:59 +0800 |
|---|---|---|
| committer | Brian Masney <bmasney@redhat.com> | 2026-07-28 11:25:30 -0400 |
| commit | 442d24ce7f4c09a7d14b949d7a6b640bd63cc4e0 (patch) | |
| tree | f5b381567735717cafca516cb9d03af3f137a9fe /include | |
| parent | 3ed463b69be8120d8f674051f0fe3304ef9839cc (diff) | |
| download | linux-442d24ce7f4c09a7d14b949d7a6b640bd63cc4e0.tar.gz linux-442d24ce7f4c09a7d14b949d7a6b640bd63cc4e0.zip | |
dt-bindings: clock: mediatek: Add mt8173 mfgtop
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.
The clock gates are exposed as clocks provided by a clock controller,
while the power sequencing bits are exposed as one singular power domain.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/mt8173-clk.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 3d00c98b9654..89e982f771db 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -243,6 +243,13 @@ #define CLK_IMG_FD 7 #define CLK_IMG_NR_CLK 8 +/* MFG_SYS */ + +#define CLK_MFG_AXI 0 +#define CLK_MFG_MEM 1 +#define CLK_MFG_G3D 2 +#define CLK_MFG_26M 3 + /* MM_SYS */ #define CLK_MM_SMI_COMMON 1 |