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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:45 +0100 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:45 +0100 |
| commit | 6b4a095cd537aade8c0e2dc1c17067e451a0cca1 (patch) | |
| tree | 4a4b6dd7d1113fff54997df02a046bf9a8b1bc45 /include | |
| parent | 9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f (diff) | |
| parent | 25458fdd39a18a5ce00c36f38992da54bb7453f3 (diff) | |
| download | linux-6b4a095cd537aade8c0e2dc1c17067e451a0cca1.tar.gz linux-6b4a095cd537aade8c0e2dc1c17067e451a0cca1.zip | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14
Renesas RZ/G3E DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047)
SoC, shared by driver and DT source files.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |