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| author | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 16:22:34 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 16:22:34 -0700 |
| commit | 763e15d04740ad2984bf009d9a5f70c099c8e6fd (patch) | |
| tree | d1d2e70d4ac33eb687d9a863684e03aad0be4d18 /include | |
| parent | d781a45270a8acabe2576cc5c47dc33180eca87c (diff) | |
| parent | 516e5bd0b6bf4ae1ad072df637b428a737c3c870 (diff) | |
| download | linux-763e15d04740ad2984bf009d9a5f70c099c8e6fd.tar.gz linux-763e15d04740ad2984bf009d9a5f70c099c8e6fd.zip | |
Merge branch 'for-6.15/extended-linear-cache' into cxl-for-next2
Add support for Extended Linear Cache for CXL. Add enumeration support
of the cache. Add MCE notification of the aliased memory address.
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/acpi.h | 11 | ||||
| -rw-r--r-- | include/linux/node.h | 7 |
2 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 4e495b29c640..cbd933504dbf 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1095,6 +1095,17 @@ static inline acpi_handle acpi_get_processor_handle(int cpu) #endif /* !CONFIG_ACPI */ +#ifdef CONFIG_ACPI_HMAT +int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid, + resource_size_t *size); +#else +static inline int hmat_get_extended_linear_cache_size(struct resource *backing_res, + int nid, resource_size_t *size) +{ + return -EOPNOTSUPP; +} +#endif + extern void arch_post_acpi_subsys_init(void); #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC diff --git a/include/linux/node.h b/include/linux/node.h index 9a881c2208b3..2b7517892230 100644 --- a/include/linux/node.h +++ b/include/linux/node.h @@ -57,6 +57,11 @@ enum cache_write_policy { NODE_CACHE_WRITE_OTHER, }; +enum cache_mode { + NODE_CACHE_ADDR_MODE_RESERVED, + NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR, +}; + /** * struct node_cache_attrs - system memory caching attributes * @@ -65,6 +70,7 @@ enum cache_write_policy { * @size: Total size of cache in bytes * @line_size: Number of bytes fetched on a cache miss * @level: The cache hierarchy level + * @address_mode: The address mode */ struct node_cache_attrs { enum cache_indexing indexing; @@ -72,6 +78,7 @@ struct node_cache_attrs { u64 size; u16 line_size; u8 level; + u16 address_mode; }; #ifdef CONFIG_HMEM_REPORTING |