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| author | Nicolin Chen <nicolinc@nvidia.com> | 2026-07-28 10:33:33 -0700 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-08-02 10:18:15 +0000 |
| commit | 773f2b9e367019c03ed18f2736c8f67307305088 (patch) | |
| tree | e103e9994e24edafc69ef98845e136bd5f39a0ff /include | |
| parent | eced8058c82a3a81ae480a6546e2da32100dddfa (diff) | |
| download | linux-773f2b9e367019c03ed18f2736c8f67307305088.tar.gz linux-773f2b9e367019c03ed18f2736c8f67307305088.zip | |
iommu/arm-smmu-v3: Support IDR5.DS and widen the TLBI SCALE field
An SMMU implementing SMMU_IDR5.DS extends the range invalidation commands:
the SCALE field grows a 6th bit, raising its maximum value from 31 to 39,
and TTL == 0b01 becomes a valid level hint for a 16KB translation granule.
Add a new ARM_SMMU_FEAT_DS feature detecting the DS bit, and widen the
CMDQ_TLBI_0_SCALE field to its architectural 6 bits. Mask the scale value
explicitly in arm_smmu_cmdq_batch_add_range(), so the range invalidation
path emits the same commands as before, keeping the pre-existing 5-bit
truncation of a scale above 31.
Also list DS as a valid IDR5 field in the iommu_hw_info_arm_smmuv3 kdoc:
iommufd has always reported the raw IDR5 register, so a VMM may conclude
from that bit alone that it can expose DS to its guest.
Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Assisted-by: Claude:claude-fable-5
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/uapi/linux/iommufd.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index f73a392b3d3f..c6851c7655c6 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -605,7 +605,7 @@ enum iommu_hw_info_arm_smmuv3_flags { * idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF * idr[1]: SIDSIZE, SSIDSIZE * idr[3]: BBML, RIL - * idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K + * idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K, DS * * - S1P should be assumed to be true if a NESTED HWPT can be created * - VFIO/iommufd only support platforms with COHACC, it should be assumed to be @@ -613,7 +613,7 @@ enum iommu_hw_info_arm_smmuv3_flags { * - ATS is a per-device property. If the VMM describes any devices as ATS * capable in ACPI/DT it should set the corresponding idr. * - * This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is + * This list may expand in future (eg E0PD, AIE, PBHA, D128 etc). It is * important that VMMs do not read bits outside the list to allow for * compatibility with future kernels. Several features in the SMMUv3 * architecture are not currently supported by the kernel for nesting: HTTU, |