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| author | Wayne Lin <Wayne.Lin@amd.com> | 2026-07-23 15:03:39 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-06 12:43:49 -0400 |
| commit | fdd9ca88783644ac5085285cebe7e8d97886d20d (patch) | |
| tree | cfdc7823194e9f4878f1114f49d9eb8b6495592a /scripts/checkstack.pl | |
| parent | f82cee9dd809aca205664d235f7c02c615ad1408 (diff) | |
| download | linux-fdd9ca88783644ac5085285cebe7e8d97886d20d.tar.gz linux-fdd9ca88783644ac5085285cebe7e8d97886d20d.zip | |
drm/amd/display: Add missing OTG_CRC1_SELECT mask for DCN3.2
[Why]
Configuring CRC engine 1 via optc35_configure_crc() triggers
ASSERT(mask != 0) in dc_helper.c when programming OTG_CRC1_SELECT.
The DCN3.2 OPTC mask list inherited from dcn32 is missing this field,
so ROI[1] CRC cannot be enabled in DisplayCRC mode on DCN3.5/3.51.
[How]
Add OTG_CRC1_SELECT to OPTC_COMMON_MASK_SH_LIST_DCN3_2, matching the
existing dcn10 definition so REG_UPDATE can program CRC engine 1.
Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions