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| author | Jesse Zhang <Jesse.Zhang@amd.com> | 2026-08-13 12:28:04 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-19 10:08:26 -0400 |
| commit | fd65d1742992361fc2201ecb4e43411e6e417fcb (patch) | |
| tree | cdfced4886abdce830687ce4980dd9453386b73c /scripts/const_structs.checkpatch | |
| parent | 556488b08638aad240bdb524cebf22fa7569843c (diff) | |
| download | linux-fd65d1742992361fc2201ecb4e43411e6e417fcb.tar.gz linux-fd65d1742992361fc2201ecb4e43411e6e417fcb.zip | |
drm/amdgpu: force complete the KIQ ring fences on reset
Like the MES scheduler ring, the KIQ ring sets no_scheduler = true and uses a
polling fence, so it is skipped by the force-completion loop in
amdgpu_device_pre_asic_reset(). Its hw fence value lives in wb (GTT) memory and
survives a MODE1 reset while fence_drv.sync_seq keeps advancing, so after a
reset the first KIQ submission can poll forever on a seq that is never written
back.
Force complete the KIQ ring fences too so their hw fence is realigned to
sync_seq.
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/const_structs.checkpatch')
0 files changed, 0 insertions, 0 deletions