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| author | Chenguang Zhao <zhaochenguang@kylinos.cn> | 2026-08-17 22:07:39 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2026-08-17 22:07:39 +0800 |
| commit | 576412d98297bd0b3b837c20643ab2e1ba54766f (patch) | |
| tree | a016448ae1c135e9e79076b44099c90a876d8b4d /scripts/stackusage | |
| parent | 9fcdba34230a4bbc5d907b5c48f23f95061ceed1 (diff) | |
| download | linux-576412d98297bd0b3b837c20643ab2e1ba54766f.tar.gz linux-576412d98297bd0b3b837c20643ab2e1ba54766f.zip | |
LoongArch: BPF: Align value-returning atomics with LKMM
Per the Linux Kernel Memory Model, value-returning atomic RMW operations
must provide sequentially consistent ordering (a full memory barrier).
On LoongArch, plain AMO instructions and bare ll/sc loops do not satisfy
this requirement by themselves.
Update emit_atomic_rmw() to emit barrier-carrying instructions for all
value-returning BPF atomics:
- BPF_FETCH (ADD/AND/OR/XOR): use am*_db.{b,h,w,d}
- BPF_XCHG: use amswap_db.{b,h,w,d}
- BPF_CMPXCHG: emit dbar 0x700 after the ll/sc loop, matching
__WEAK_LLSC_MB in cmpxchg.h
Add the corresponding instruction encodings and emit helpers to inst.h.
Non-value-returning RMW ops (plain BPF_ADD, BPF_AND, etc.) are left as
weakly ordered, consistent with LKMM.
Acked-by: Hengqi Chen <hengqi.chen@gmail.com>
Acked-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Chenguang Zhao <zhaochenguang@kylinos.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions
