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authorJames Hilliard <james.hilliard1@gmail.com>2026-07-17 10:41:58 -0600
committerMiquel Raynal <miquel.raynal@bootlin.com>2026-08-07 15:54:29 +0200
commit5ee37db34637ca6e33ce01d7062cb31275484404 (patch)
tree3743cff25354838f5e291982f3a1e007279c808d /scripts/stackusage
parent8211f2d74b356a02fe38aeea5b74030ac156461f (diff)
downloadlinux-5ee37db34637ca6e33ce01d7062cb31275484404.tar.gz
linux-5ee37db34637ca6e33ce01d7062cb31275484404.zip
mtd: rawnand: sunxi: add H616 MBUS DMA support
The H616 NAND controller uses a descriptor-based internal MBUS DMA engine instead of the direct address and count registers used by the A23/A33 controller. Since the driver does not support these descriptors, it currently attempts to request an external rxtx DMA channel and falls back to PIO when none is provided. Add a single-descriptor backend to the existing ECC page DMA paths. Allocate the descriptor coherently, constrain data mappings to the controller's 32-bit address range, program the H6-style data block mask, and request an interrupt for both command and DMA completion. Keep the existing external DMA and legacy MBUS DMA paths unchanged, and fall back to PIO if the descriptor cannot be allocated. With identical kernels except for this patch, running flash_speed -d -b 1906 -c 100 /dev/mtd6 on an H616 board with 2 KiB-page SLC NAND reported: PIO descriptor DMA eraseblock write 3365 KiB/s 4192 KiB/s eraseblock read 6454 KiB/s 16040 KiB/s page write 3254 KiB/s 4021 KiB/s page read 6419 KiB/s 15686 KiB/s Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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