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| author | Thierry Reding <treding@nvidia.com> | 2026-08-14 17:38:55 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-08-19 12:08:15 -0500 |
| commit | d86c91afe28b4666b6d8dd86c25d25235f88eebc (patch) | |
| tree | 3b1a72bc30db2c6f4b5edb81844e4f3355178676 /scripts | |
| parent | 071e245ab749c52338ec4eb7fe0a9bb2cee97492 (diff) | |
| download | linux-d86c91afe28b4666b6d8dd86c25d25235f88eebc.tar.gz linux-d86c91afe28b4666b6d8dd86c25d25235f88eebc.zip | |
dt-bindings: PCI: tegra264: Strictly distinguish C0 from C1-C5
Instead of using the ECAM registers as the first entry, strictly make a
distinction between C0 and C1-C5. This is needed because otherwise the
unit address doesn't match the first "reg" entry. The ordering of these
nodes cannot be changed to follow the ECAM addresses because that would
put them outside of their "control bus" hierarchy since the ECAM address
space is a global one outside of any of the control busses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260814-tegra264-pcie-v10-1-05d08c592b05@nvidia.com
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions