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| author | Kaiwen Xue <kaiwenx@rivosinc.com> | 2026-08-07 19:24:31 -0600 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-08-07 19:24:31 -0600 |
| commit | 09b5f358e85376c1e014bd8ea9d6806754d659e7 (patch) | |
| tree | 6c4e13d51f48d691307e9c4689d6ab4b955f86d1 /tools/lib/python | |
| parent | e24a1418e90beac2ef4384bc9b0b5a10f19b806e (diff) | |
| download | linux-09b5f358e85376c1e014bd8ea9d6806754d659e7.tar.gz linux-09b5f358e85376c1e014bd8ea9d6806754d659e7.zip | |
RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions
This adds definitions of new CSRs and bits defined in the Smcsrind and
Sscsrind ISA extensions. These CSRs enable the indirect CSR accesses
mechanism to access any indirect CSRs in M-, S-, and VS-mode. The
range of the select values and ireg will be defined by the ISA
extension that are based on the Smcsrind and Sscsrind extensions.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
[pjw@kernel.org: clean up the patch description; use official RISC-V extension names]
Link: https://patch.msgid.link/20260807-counter_delegation-v9-2-58658104e487@meta.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions