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| author | Sascha Bischoff <Sascha.Bischoff@arm.com> | 2026-08-11 15:27:00 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-08-20 10:23:53 +0200 |
| commit | 3dfc0ab5fefd052c6028c4632b1fad8bdaf7967e (patch) | |
| tree | c8020c349de67674a178fa495f9f3e23484b11c0 /tools/lib/python | |
| parent | 34b7e953d19a39515f8fc6c0820ebf243ea6b026 (diff) | |
| download | linux-3dfc0ab5fefd052c6028c4632b1fad8bdaf7967e.tar.gz linux-3dfc0ab5fefd052c6028c4632b1fad8bdaf7967e.zip | |
irqchip/gic-v5: Clear per-CPU IRS data on teardown
IRS affinity setup publishes an IRS pointer and IAFFID state in the
per-CPU data before the remaining IRS initialization can fail. The
error path then frees the IRS data without clearing that published
state, leaving CPUs associated with freed memory.
On initialization failure and normal IRS teardown, clear the per-CPU
IRS association by removing the stale pointer to irs_data. Also
invalidate the per-CPU IAFFID state for any CPUs that were tied to the
IRS before it was freed.
Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
Fixes: 35866efa52fe ("irqchip/gic-v5: Add ACPI IRS probing")
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=2
Link: https://patch.msgid.link/20260811152630.942023-2-sascha.bischoff@arm.com
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions