summaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python
diff options
context:
space:
mode:
authorJiawen Wu <jiawenwu@trustnetic.com>2026-08-24 15:21:19 +0800
committerPaolo Abeni <pabeni@redhat.com>2026-08-27 12:15:08 +0200
commit63c885688f38a757947d7050b1ee4171215269ce (patch)
treee5fe5f69761a6255670b1081b62af90ee4b1badd /tools/perf/scripts/python
parentea30dc5267e367b8a5e1e06cc074f813bcbf18b2 (diff)
downloadlinux-63c885688f38a757947d7050b1ee4171215269ce.tar.gz
linux-63c885688f38a757947d7050b1ee4171215269ce.zip
net: wangxun: use BIT_ULL() to prevent shift overflow on 32-bit archs
The macros TXGBE_INTR_MISC() and WX_INTR_Q() rely on the standard BIT() macro to generate interrupt masks based on the queue vector index. On 32-bit architectures, BIT() evaluates to a 32-bit `unsigned long`. Since the number of queue vectors can be up to 63 on txgbe devices, performing a left shift of 32 or more results in an integer overflow and undefined behavior. This causes incorrect interrupt masking and unmasking logic for both the queue and miscellaneous interrupts on 32-bit systems. Fix this by replacing BIT() with BIT_ULL() in these macros. This ensures that the bitwise shift is always performed safely on a 64-bit `unsigned long long` type, regardless of the underlying architecture. Fixes: e37546ad1f9b ("net: wangxun: revert the adjustment of the IRQ vector sequence") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Link: https://patch.msgid.link/45F5565CE6AC4329+20260824072119.48399-1-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions