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authorDapeng Mi <dapeng1.mi@linux.intel.com>2026-07-08 13:32:26 +0800
committerNamhyung Kim <namhyung@kernel.org>2026-07-15 11:16:40 -0700
commitea46211d7e9a2210b62c40e56b2d6540c0b4b083 (patch)
tree006374a50907d124f25cc08d1179e399d00285de /tools
parent17e3978f3ad1c6c4c9aca009a5081c6b0ebb5491 (diff)
downloadlinux-ea46211d7e9a2210b62c40e56b2d6540c0b4b083.tar.gz
linux-ea46211d7e9a2210b62c40e56b2d6540c0b4b083.zip
perf jevents: Add Intel OMR MSR mappings
New OMR MSRs are introduced for OMR events on DMR and NVL. Perf continues to reuse the existing offcore_rsp attribute to encode the MSR value, similar to existing OCR event handling. Add the corresponding OMR MSR mappings in lookup_msr() so jevents can translate these events and generate the correct offcore_rsp attribute. Link: https://lore.kernel.org/all/20260114011750.350569-2-dapeng1.mi@linux.intel.com/ Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Diffstat (limited to 'tools')
-rwxr-xr-xtools/perf/pmu-events/jevents.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 376dc2d24162..2bb51cc621b5 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -249,6 +249,10 @@ class JsonEvent:
0x3F6: 'ldlat=',
0x1A6: 'offcore_rsp=',
0x1A7: 'offcore_rsp=',
+ 0x3E0: 'offcore_rsp=',
+ 0x3E1: 'offcore_rsp=',
+ 0x3E2: 'offcore_rsp=',
+ 0x3E3: 'offcore_rsp=',
0x3F7: 'frontend=',
}
return msrmap[int(num.split(',', 1)[0], 0)]