diff options
17 files changed, 742 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index cb55c6b70d0e..761d82b4f4f2 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -206,6 +206,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo @@ -321,6 +323,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ rk3588-rock-5b-pcie-srns.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-4k-cam.dtb +rk3588-rock-5b-plus-radxa-4k-cam-dtbs := rk3588-rock-5b-plus.dtb \ + rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo \ + rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ rk3588-tiger-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts index b76f98962076..e366f1a04b32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts @@ -16,7 +16,7 @@ &i2c2 { eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; + compatible = "microchip,24aa025e48"; reg = <0x51>; pagesize = <16>; size = <256>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index 3a9a10f531bd..4274d1b6e80a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -66,16 +66,41 @@ status = "disabled"; }; +/* No USB type-C PD power manager */ +/delete-node/ &fusb0; + +&i2c1 { + status = "disabled"; +}; + &i2c4 { status = "disabled"; }; +&i2c7 { + status = "disabled"; +}; + +&i2s2 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + &pcie0 { num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; }; &pinctrl { + /delete-node/ fusb30x; + gpio-leds { /delete-node/ status-led-pin; @@ -101,14 +126,21 @@ }; }; +&pwm0 { + status = "disabled"; +}; + &sdhci { status = "disabled"; }; &sdio0 { + /delete-property/ mmc-pwrseq; status = "disabled"; }; +/delete-node/ &sdio_pwrseq; + &u2phy0_host { phy-supply = <&vdd_5v>; }; @@ -119,12 +151,48 @@ &uart0 { status = "disabled"; + + /delete-node/ bluetooth; }; +&u2phy1_host { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; &usbdrd_dwc3_0 { dr_mode = "host"; }; +/delete-node/ &vbus_typec; + &vcc3v3_sys { vin-supply = <&vcc5v0_sys>; }; + +&vopb { + status = "disabled"; +}; + +&vopb_mmu { + status = "disabled"; +}; + +&vopl { + status = "disabled"; +}; + +&vopl_mmu { + status = "disabled"; +}; + +/delete-node/ &bt_host_wake_l; +/delete-node/ &bt_reg_on_h; +/delete-node/ &bt_wake_l; +/delete-node/ &wifi_reg_on_h; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index b5c05928142c..f21fcdc1b49a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -526,7 +526,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; regulator-state-mem { regulator-on-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index c41af8fc0c8d..ee4183fb980d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -480,3 +480,28 @@ vddio-supply = <&vcc_1v8>; }; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts index 9f683033c5f3..97d85124d21b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts @@ -338,3 +338,32 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&usb2_host_5v>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index b32452756155..f872b8d20ebc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -134,6 +134,18 @@ regulator-max-microvolt = <5000000>; }; + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + vccio_sd: regulator-vccio-sd { compatible = "regulator-gpio"; gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; @@ -273,6 +285,12 @@ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -320,3 +338,45 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* + * The usb controller can only work in peripheral mode, as it is + * connected to one of the ports of an outward-facing usb hub. + * + * type_c-port (hub-input) + * | + * usb-hub + * | | + * uart-usb usb-host0 + * | + * uart0 + */ +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi index aedc7ee9ee46..501a91f4c23e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi @@ -166,6 +166,10 @@ }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -291,3 +295,16 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts index 0b696d49b71f..5e17ec2758d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts @@ -79,3 +79,14 @@ }; }; }; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb30_otg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts index 3e2b9b685cb2..f2b021ff5046 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts @@ -8,3 +8,15 @@ model = "Radxa ROCK 2F"; compatible = "radxa,rock-2f", "rockchip,rk3528"; }; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 77d314716b43..03cd00f88dbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -336,6 +336,33 @@ }; }; + usb_host0_xhci: usb@fe500000 { + compatible = "rockchip,rk3528-dwc3", "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG>, + <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_A_USB3OTG>; + dr_mode = "otg"; + phys = <&usb2phy_otg>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis_rxdet_inp3_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + gic: interrupt-controller@fed01000 { compatible = "arm,gic-400"; reg = <0x0 0xfed01000 0 0x1000>, @@ -349,6 +376,30 @@ #interrupt-cells = <3>; }; + usb_host0_ehci: usb@ff100000 { + compatible = "generic-ehci"; + reg = <0x0 0xff100000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff140000 { + compatible = "generic-ohci"; + reg = <0x0 0xff140000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + qos_crypto_a: qos@ff200000 { compatible = "rockchip,rk3528-qos", "syscon"; reg = <0x0 0xff200000 0x0 0x20>; @@ -1281,6 +1332,35 @@ rockchip,pipe-phy-grf = <&pipe_phy_grf>; status = "disabled"; }; + + usb2phy: usb2phy@ffdf0000 { + compatible = "rockchip,rk3528-usb2phy"; + reg = <0x0 0xffdf0000 0x0 0x10000>; + clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy_480m"; + power-domains = <&power RK3528_PD_VO>; + rockchip,usbgrf = <&vo_grf>; + status = "disabled"; + + usb2phy_otg: otg-port { + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_host: host-port { + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 98cfa3abb809..a091c3a44747 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; +#include <dt-bindings/input/input.h> #include "rk3568-radxa-cm3i.dtsi" / { @@ -11,6 +12,19 @@ mmc1 = &sdmmc0; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + pwm-leds { compatible = "pwm-leds-multicolor"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b..a5832895bd39 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -195,7 +195,8 @@ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index e7fe22eb31a3..3121a0ba7c7c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -30,6 +30,29 @@ }; }; + vcc5v0_device: regulator-vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_device>; + }; + vcc_sys: regulator-vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -78,6 +101,10 @@ status = "okay"; }; +&combphy1_psu { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -525,12 +552,32 @@ }; &pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; @@ -552,10 +599,45 @@ status = "okay"; }; +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart0 { status = "okay"; }; +&uart5 { + pinctrl-0 = <&uart5m1_xfer &uart5m1_ctsn &uart5m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + &vop { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4535e0b6e979..a22da6671da3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,6 +1262,50 @@ #iommu-cells = <0>; }; + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb60000 0x0 0x200>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb70000 0x0 0x200>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA31>; + }; + rga: rga@fdb80000 { compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; reg = <0x0 0xfdb80000 0x0 0x180>; @@ -1430,6 +1474,89 @@ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + vicap: video-capture@fdce0000 { + compatible = "rockchip,rk3588-vicap"; + reg = <0x0 0xfdce0000 0x0 0x800>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>, + <&cru ICLK_CSIHOST1>; + clock-names = "aclk", "hclk", "dclk", "iclk", "iclk1"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>, + <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, + <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, + <&cru SRST_CSIHOST5_VICAP>; + reset-names = "arst", "hrst", "drst", "irst0", "irst1", + "irst2", "irst3", "irst4", "irst5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0x0>; + }; + + vicap_mipi0: port@1 { + reg = <0x1>; + }; + + vicap_mipi1: port@2 { + reg = <0x2>; + }; + + vicap_mipi2: port@3 { + reg = <0x3>; + + vicap_mipi2_input: endpoint { + remote-endpoint = <&csi2_output>; + }; + }; + + vicap_mipi3: port@4 { + reg = <0x4>; + }; + + vicap_mipi4: port@5 { + reg = <0x5>; + + vicap_mipi4_input: endpoint { + remote-endpoint = <&csi4_output>; + }; + }; + + vicap_mipi5: port@6 { + reg = <0x6>; + }; + + vicap_toisp0: port@10 { + reg = <0x10>; + }; + + vicap_toisp1: port@11 { + reg = <0x11>; + }; + }; + }; + + vicap_mmu: iommu@fdce0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1452,6 +1579,10 @@ csi2_out: port@1 { reg = <1>; + + csi2_output: endpoint { + remote-endpoint = <&vicap_mipi2_input>; + }; }; }; }; @@ -1478,6 +1609,10 @@ csi4_out: port@1 { reg = <1>; + + csi4_output: endpoint { + remote-endpoint = <&vicap_mipi4_input>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso new file mode 100644 index 000000000000..ee9ecf68a886 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM0 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + savdd_cam0: regulator-savdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam0: regulator-sdvdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam0"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam0: regulator-siovdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam0>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + dvdd-supply = <&sdvdd_cam0>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_rstn &mipim0_camera3_clk>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + + port { + imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi2_input>; + }; + }; + }; +}; + +&pinctrl { + cam0 { + cam0_rstn: cam0-rstn-pinctrl { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi2 { + status = "okay"; +}; + +&csi2_in { + csi2_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&imx415_output>; + }; +}; + +&csi_dphy0 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso new file mode 100644 index 000000000000..8a4cf3fdbf8e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM1 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + savdd_cam1: regulator-savdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam1: regulator-sdvdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam1"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam1: regulator-siovdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam1_imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam1>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + dvdd-supply = <&sdvdd_cam1>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam1>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_rstn &mipim0_camera4_clk>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + + port { + cam1_imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi4_input>; + }; + }; + }; +}; + +&pinctrl { + cam1 { + cam1_rstn: cam1-rstn-pinctrl { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi4 { + status = "okay"; +}; + +&csi4_in { + csi4_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&cam1_imx415_output>; + }; +}; + +&csi_dphy1 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; |