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2026-06-23Merge tag 'phy-for-7.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Bunch of new driver, device support in existing drivers/binding and few updates to existing drivers New Support: - Qualcomm Eliza QMP PHY, Eliza Synopsys eUSB2 support, Eliza PCIe phy support, Nord QMP UFS PHY, IPQ5210 USB3 PHY support - Econet EN751221 and EN7528 PCIe phy support - NXPs TJA1145 CAN transceiver phy support - TI DS125DF111 retimer phy support - Rockchip RK3528 usb phy support - TI J722S phy support - Axiado eMMC PHY driver - EyeQ5 Ethernet PHY driver - Generic PHY driver for Lynx 10G SerDes - Spacemit K3 USB2 PHY support Updates: - Tomi helping maintian zynqmp phys - lynx phy updates to support 25GBASER - Rockchip GRF for RK3568/RV1108 support - Qualcomm QSERDES COM v2 support" * tag 'phy-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (87 commits) phy: rockchip: inno-usb2: Add missing clkout_ctl_phy kerneldoc phy: Move MODULE_DEVICE_TABLE next to the table itself phy: add basic support for NXPs TJA1145 CAN transceiver dt-bindings: phy: add support for NXPs TJA1145 CAN transceiver phy: freescale: phy-fsl-imx8qm-lvds-phy: Fix missing pm_runtime_disable() on probe error path dt-bindings: phy: qcom,qmp-usb: Add ipq5210 USB3 PHY dt-bindings: phy: qcom,qusb2: Document IPQ5210 compatible phy: freescale: phy-fsl-imx8qm-lvds-phy: Use synchronous PM runtime put in reset MAINTAINERS: expand Lynx 28G entry to cover Lynx 10G SerDes phy: lynx-10g: new driver dt-bindings: phy: lynx-10g: initial document phy: lynx-28g: improve phy_validate() procedure phy: lynx-28g: optimize read-modify-write operation phy: lynx-28g: add support for big endian register maps phy: lynx-28g: common probe() and remove() phy: lynx-28g: make lynx_28g_pll_read_configuration() callable per PLL phy: lynx-28g: move struct lynx_info definitions downwards phy: lynx-28g: provide default lynx_lane_supports_mode() implementation phy: lynx-28g: generalize protocol converter accessors phy: lynx-28g: common lynx_pll_get() ...
2026-06-11dt-bindings: phy: add support for NXPs TJA1145 CAN transceiverDimitri Fedrau
Adding documentation for NXPs TJA1145 CAN transceiver, which resides like the ti,tcan104x-can.yaml in the same directory as other generic PHY subsystem bindings. At the moment there is only support for simple PHYs by using regulator bindings in combination with can-transceiver.yaml or PHYs that implement the generic PHY subsystem like the NXP TJA1145. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com> Link: https://patch.msgid.link/20260602-tja1145-support-v6-1-0e0ffc8ee63d@liebherr.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: qcom,qmp-usb: Add ipq5210 USB3 PHYVaradarajan Narayanan
Add dt-bindings for the USB3 QMP PHY found on the Qualcomm IPQ5210 SoC. The IPQ5210 PHY is compatible with the IPQ9574 PHY, so add it as a fallback- compatible entry using a oneOf construct rather than a plain enum entry. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260608103344.2740174-3-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: qcom,qusb2: Document IPQ5210 compatibleVaradarajan Narayanan
Document the QUSB2 PHY compatible for the IPQ5210 SoC. The IPQ5210 PHY is compatible with the IPQ6018 QUSB2 PHY, so allow it to use qcom,ipq6018-qusb2-phy as the fallback compatible. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260608103344.2740174-2-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: lynx-10g: initial documentVladimir Oltean
Add a schema for the 10G Lynx SerDes. This is very similar to the modern form of the 28G Lynx SerDes, which is very much the intention. There is intentionally no generic fsl,lynx-10g compatible string due to the hardware inability to report its capabilities, despite having a common register map. We allow both forms of #phy-cells = <1> in the top-level provider and #phy-cells = <0> in the per-lane provider for more flexibility to consumers, and because the kernel code is shared with the 28G Lynx which already has that support for compatibility reasons. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260610151952.2141019-15-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: sc8280xp-qmp-pcie: Document Eliza PCIe phyKrishna Chaitanya Chundru
Add compatibles for the Eliza PCIe QMP PHY's, which supports Gen3x1 and Gen3x2 configurations. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260608-eliza-v3-1-9bdeb7434b28@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: sc8280xp-qmp-pcie: Disallow bifurcation register on PurwaKonrad Dybcio
Neither of the two Gen4x4 PHYs found on Purwa supports bifurcation. The PHY is however physically laid out as if it were to, since there are two separate ports (A/B). Split out a new if-then block to un-require the bifurcation register handle to squash this warning: purwa-iot-evk.dtb: phy@1bd4000 (qcom,x1p42100-qmp-gen4x4-pcie-phy): 'qcom,4ln-config-sel' is a required property Fixes: 2e1ffd4c1805 ("dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY") Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/linux-arm-msm/176857775469.1631885.16133311938753588148.robh@kernel.org/ Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260610-topic-purwa_phy_shutup_warning-v2-1-951c1fbfe9b2@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-22dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHYLuca Weiss
Document the DSI PHY on the Milos Platform. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Patchwork: https://patchwork.freedesktop.org/patch/722309/ Link: https://lore.kernel.org/r/20260501-milos-mdss-v3-1-58bfc58c0e13@fairphone.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-19dt-bindings: phy: add PHY bindings for the TI DS125DF111 Retimer PHYIoana Ciornei
Add device tree binding for the TI DS125DF111 Retimer PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260518142026.3098496-2-ioana.ciornei@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-14dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528Caleb James DeLisle
EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY which behaves slightly differently because one slot is Gen1/Gen2 while the other is Gen1 only. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260425173642.406089-2-cjd@cjdns.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-14dt-bindings: phy: rockchip,inno-usb2phy: Add compatible for RK3528Jonas Karlman
The embedded USB2 PHY on RK3528 is very similar to the one in RK3568, the main difference being that it only uses two clocks instead of three. Add compatible to support the USB2 PHY in RK3528. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260505170410.3265305-4-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-14dt-bindings: phy: rockchip,inno-usb2phy: Require GRF for RK3568/RV1108Jonas Karlman
Typically these Rockchip USB2 PHYs are fully contained within a single GRF. However, for RK3568 and RV1108 regs to control the USB2 PHY is located in a different GRF compared to the base address. Update this binding to require rockchip,usbgrf for RK3568 and RV1108 to properly reflect that the USB GRF is required to control the USB2 PHYs on these variants. Also disable use of rockchip,usbgrf for variants where it is not required. This should not introduce any breakage as the affected usb2phy nodes for RK3568 and RV1108 were added together with a rockchip,usbgrf phandle in their initial commit. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260505170410.3265305-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-14dt-bindings: phy: lynx-28g: add constraint on LX2162A lane indicesVladimir Oltean
The SerDes 1 of LX2162A has fewer lanes than all other instances, and strangely, their indices are not 0-3, but 4-7. This is a best-effort constraint, since we can only impose it when using per-SoC compatible string and per-lane OF nodes. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Josua Mayer <josua@solid-run.com> Link: https://patch.msgid.link/20260511150023.1903577-3-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-14dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiationVladimir Oltean
The 28G Lynx SerDes is instantiated 3 times in the NXP LX2160A SoC and twice in the NXP LX2162A. All these instances share the same register map, but the number of lanes and the protocols supported by each lane differs in a way that isn't detectable by the programming model. For example, not all lanes of all SerDes block instantiations support 25GbE. So, using a generic "fsl,lynx-28g" compatible string and expecting all SerDes instantiations to use it was a mistake that needs to be fixed. The option chosen is to encode the SoC and the SerDes instance in the compatible string, with everything else being the responsibility of the driver to derive. An alternative considered but dismissed was to add sufficient device tree properties to describe the per-lane differences (implying: supported protocols), as well as the different lane count. Any decision made for the 28G Lynx should be consistent with the decisions taken for the yet-to-be-introduced 10G Lynx SerDes (older generation for older SoCs), because of how similar they are. I've seen the alternative at play in this unmerged patch set for the 10G Lynx here, and I didn't like it: https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@seco.com/ This is because there, we have a higher degree of variability in the PCCR register values that need to be written per protocol. This makes that approach more drawn-out and more prone to errors, compared to the compatible strings which are more succinct and obviously correct. NXP SoC reference manuals clearly document the SerDes instantiations as not identical, and refers to them as such (SerDes 1, 2, etc). The per-SoC compatible string is prepended to the "fsl,lynx-28g" generic compatible, which is left there for compatibility with old kernels. An exception would be LX2160A SerDes #3, which at the time of writing is not described in fsl-lx2160a.dtsi. As "fsl,lx2160a-serdes3" implies it is a 28G Lynx SerDes, it makes "fsl,lynx-28g" redundant so we don't accept it. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Josua Mayer <josua@solid-run.com> Link: https://patch.msgid.link/20260511150023.1903577-2-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHYRitesh Kumar
The initial sa8775p eDP PHY binding contribution missed adding support for voting on the eDP reference clock. This went unnoticed because the UFS PHY driver happened to enable the same clock. After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off calls"), the eDP reference clock is no longer kept enabled, which results in the following PHY power-on failure: phy phy-aec2a00.phy.10: phy poweron failed --> -110 To fix this, explicit voting for the eDP reference clock is required. This patch adds the eDP reference clock for sa8775p eDP PHY and updates the corresponding example node. Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260128114853.2543416-2-quic_riteshk@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHYSriNavmani A
Axiado AX3000 SoC contains Arasan PHY which provides the interface to the HS200 eMMC host controller. Signed-off-by: SriNavmani A <srinavmani@axiado.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Tzu-Hao Wei <twei@axiado.com> Link: https://patch.msgid.link/20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-1-3ab7eb45b0c5@axiado.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHYAbel Vesa
Document the compatible for the USB QMP PHY found on the Qualcomm Eliza SoC. It is fully compatible with the one found on Qualcomm SM8650, so add it with the SM8650 as fallback. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260504-eliza-bindings-qmp-phy-v2-1-849c4de8d75f@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHYAbel Vesa
The Synopsys eUSB2 PHY found on the Eliza SoC is fully compatible with the one found the SM8550. So document it by adding the compatible to the list that has the SM8550 one as fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260504-eliza-bindings-phy-eusb2-v2-1-fa3a1fd65ab1@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHYShawn Guo
Document QMP UFS PHY on Qualcomm Nord SoC. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260504081442.825908-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: spacemit: k3: add USB2 PHY supportYixun Lan
Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP of USB2 PHY mostly shares the same functionalities with K1 SoC, while has some register layout changes. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1] Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2] Link: https://patch.msgid.link/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel compatibleNora Schiffer
The J722S gmii-sel is mostly identical to the AM64's, but additionally supports SGMII. The AM64 compatible ti,am654-phy-gmii-sel is used as a fallback. Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/b67c8b0bc9cc918667e9329d79f617d033d025d5.1775559102.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatibleNora Schiffer
The J722S WIZ is mostly identical to the AM64's, but additionally supports SGMII. The AM64 compatible ti,am64-wiz-10g is used as a fallback. Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/1ef8adf850f2fd41b6c4e3c89e4f4e6e0f469a0e.1775559102.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-04-17Merge tag 'phy-for-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Qualcomm Eliza QMP UFS PHY - Canaan K230 USB 2.0 PHY driver - Mediatek mt8167 dsi-phy - Eswin EIC7700 SATA PHY driver Updates: - Sorted subsytem Makefile/Kconfig and some kernel-doc udpates" * tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY phy: qcom: m31-eusb2: clear PLL_EN during init phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY phy: apple: apple: Use local variable for ioremap return value phy: qcom: qmp-usbc: Simplify check for non-NULL pointer phy: marvell: mmp3-hsic: Avoid re-casting __iomem phy: apple: atc: Make atcphy_dwc3_reset_ops variable static dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167 phy: usb: Add driver for Canaan K230 USB 2.0 PHY dt-bindings: phy: Add Canaan K230 USB PHY phy: phy-mtk-tphy: Update names and format of kernel-doc comments phy: Sort the subsystem Kconfig phy: Sort the subsystem Makefile phy: move spacemit pcie driver to its subfolder
2026-04-16Merge tag 'soc-drivers-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
2026-04-03Merge tag 'drm-msm-next-2026-04-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-next Changes for v7.1 CI: - Uprev mesa - Restore CI jobs for Qualcomm APQ8016 and APQ8096 devices Core: - Switched to of_get_available_child_by_name() DPU: - Fixes for DSC panels - Fixed brownout because of the frequency / OPP mismatch - Quad pipe preparation (not enabled yet) - Switched to virtual planes by default - Dropped VBIF_NRT support - Added support for Eliza platform - Reworked alpha handling - Switched to correct CWB definitions on Eliza - Dropped dummy INTF_0 on MSM8953 - Corrected INTFs related to DP-MST DP: - Removed debug prints looking into PHY internals DSI: - Fixes for DSC panels - RGB101010 support - Support for SC8280XP - Moved PHY bindings from display/ to phy/ GPU: - Preemption support for x2-85 and a840 - IFPC support for a840 - SKU detection support for x2-85 and a840 - Expose AQE support (VK ray-pipeline) - Avoid locking in VM_BIND fence signaling path - Fix to avoid reclaim in GPU snapshot path - Disallow foreign mapping of _NO_SHARE BOs - Couple a6xx gpu snapshot fixes - Various other fixes HDMI: - Fixed infoframes programming MDP5: - Dropped support for MSM8974v1 - Dropped now unused code for MSM8974 v1 and SDM660 / MSM8998 Also misc small fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV012vn73BaUfk=Hw4WkQHZNPHiqfifWEunAqMc2EGOWUEQ@mail.gmail.com
2026-04-01dt-bindings: display/msm: move DSI PHY bindings to phy/ subdirDmitry Baryshkov
Historically DSI PHY bindings landed to the display/msm subdir, however they describe PHYs and as such they should be in the phy/ subdir. Follow the example of other Qualcomm display-related PHYs (HDMI, eDP) and move bindings for the Qualcomm DSI PHYs to the correct subdir. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/709008/ Link: https://lore.kernel.org/r/20260305-msm-dsi-phy-v1-1-0a99ac665995@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-27dt-bindings: phy: tegra: Document Tegra210 USB PHYThierry Reding
Add a compatible string for the USB PHY found on Tegra210 SoCs. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-03-27dt-bindings: phy: tegra-xusb: Document Type C supportThierry Reding
Each XUSB PHY can be hooked up to a Type C controller via a port property, so document this in the bindings accordingly. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-03-22dt-bindings: phy: mediatek, dsi-phy: Add support for mt8167Luca Leonardo Scorcia
Add support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC. Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/92530e0a31eca1feb822f5c5fd4ac894937dd6c7.1771863641.git.l.scorcia@gmail.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-02-27dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHYAbel Vesa
Document the QMP UFS PHY compatible for the Eliza Platform. It is fully compatible with the PHY implemented in SM8650, so use the SM8650 compatible as fallback. While at it, move the QCS8300 one so that it is sorted correctly by fallback compatible. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260223-eliza-bindings-phy-ufs-v3-1-2b0c0f00bcb6@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-27dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHYYulin Lu
Document the SATA PHY on the EIC7700 SoC platform, describing its usage. Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260205082129.1482-1-luyulin@eswincomputing.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-27dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167Luca Leonardo Scorcia
Add support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC. Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patch.msgid.link/92530e0a31eca1feb822f5c5fd4ac894937dd6c7.1771863641.git.l.scorcia@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-27dt-bindings: phy: Add Canaan K230 USB PHYJiayu Du
K230 SoC USB PHY requires configuring registers for control and configuration. Add USB phy bindings for K230 SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn> Link: https://patch.msgid.link/20260121145526.14672-2-jiayu.riscv@isrc.iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-17Merge tag 'phy-for-7.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Core: - Add suuport for "rx-polarity" and "tx-polarity" device tree properties and phy common properties to manage this New Support: - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for that. - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver. - HDMI 2.1 FRL configuration support and driver enabling for rockchip samsung-hdptx driver - TI TCAN1046 phy - Renesas RZ/V2H(P) and RZ/V2N usb3 - Mediatek MT8188 hdmi-phy - Google Tensor SoC USB PHY driver - Apple Type-C PHY Updates: - Subsystem conversion for clock round_rate() to determine_rate() - TI USB3 DT schema conversion - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support" * tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits) phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate() dt-bindings: phy: ti,control-phy-otghs: convert to DT schema dt-bindings: phy: ti,phy-usb3: convert to DT schema phy: tegra: xusb: Remove unused powered_on variable phy: renesas: rcar-gen3-usb2: add regulator dependency phy: GOOGLE_USB: add TYPEC dependency phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable() phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC dt-bindings: phy: renesas,usb2-phy: Document mux-states property dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config phy: rockchip: samsung-hdptx: Drop hw_rate driver data phy: rockchip: samsung-hdptx: Compute clk rate from PLL config phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists ...
2026-02-11Merge tag 'net-next-7.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Paolo Abeni: "Core & protocols: - A significant effort all around the stack to guide the compiler to make the right choice when inlining code, to avoid unneeded calls for small helper and stack canary overhead in the fast-path. This generates better and faster code with very small or no text size increases, as in many cases the call generated more code than the actual inlined helper. - Extend AccECN implementation so that is now functionally complete, also allow the user-space enabling it on a per network namespace basis. - Add support for memory providers with large (above 4K) rx buffer. Paired with hw-gro, larger rx buffer sizes reduce the number of buffers traversing the stack, dincreasing single stream CPU usage by up to ~30%. - Do not add HBH header to Big TCP GSO packets. This simplifies the RX path, the TX path and the NIC drivers, and is possible because user-space taps can now interpret correctly such packets without the HBH hint. - Allow IPv6 routes to be configured with a gateway address that is resolved out of a different interface than the one specified, aligning IPv6 to IPv4 behavior. - Multi-queue aware sch_cake. This makes it possible to scale the rate shaper of sch_cake across multiple CPUs, while still enforcing a single global rate on the interface. - Add support for the nbcon (new buffer console) infrastructure to netconsole, enabling lock-free, priority-based console operations that are safer in crash scenarios. - Improve the TCP ipv6 output path to cache the flow information, saving cpu cycles, reducing cache line misses and stack use. - Improve netfilter packet tracker to resolve clashes for most protocols, avoiding unneeded drops on rare occasions. - Add IP6IP6 tunneling acceleration to the flowtable infrastructure. - Reduce tcp socket size by one cache line. - Notify neighbour changes atomically, avoiding inconsistencies between the notification sequence and the actual states sequence. - Add vsock namespace support, allowing complete isolation of vsocks across different network namespaces. - Improve xsk generic performances with cache-alignment-oriented optimizations. - Support netconsole automatic target recovery, allowing netconsole to reestablish targets when underlying low-level interface comes back online. Driver API: - Support for switching the working mode (automatic vs manual) of a DPLL device via netlink. - Introduce PHY ports representation to expose multiple front-facing media ports over a single MAC. - Introduce "rx-polarity" and "tx-polarity" device tree properties, to generalize polarity inversion requirements for differential signaling. - Add helper to create, prepare and enable managed clocks. Device drivers: - Add Huawei hinic3 PF etherner driver. - Add DWMAC glue driver for Motorcomm YT6801 PCIe ethernet controller. - Add ethernet driver for MaxLinear MxL862xx switches - Remove parallel-port Ethernet driver. - Convert existing driver timestamp configuration reporting to hwtstamp_get and remove legacy ioctl(). - Convert existing drivers to .get_rx_ring_count(), simplifing the RX ring count retrieval. Also remove the legacy fallback path. - Ethernet high-speed NICs: - Broadcom (bnxt, bng): - bnxt: add FW interface update to support FEC stats histogram and NVRAM defragmentation - bng: add TSO and H/W GRO support - nVidia/Mellanox (mlx5): - improve latency of channel restart operations, reducing the used H/W resources - add TSO support for UDP over GRE over VLAN - add flow counters support for hardware steering (HWS) rules - use a static memory area to store headers for H/W GRO, leading to 12% RX tput improvement - Intel (100G, ice, idpf): - ice: reorganizes layout of Tx and Rx rings for cacheline locality and utilizes __cacheline_group* macros on the new layouts - ice: introduces Synchronous Ethernet (SyncE) support - Meta (fbnic): - adds debugfs for firmware mailbox and tx/rx rings vectors - Ethernet virtual: - geneve: introduce GRO/GSO support for double UDP encapsulation - Ethernet NICs consumer, and embedded: - Synopsys (stmmac): - some code refactoring and cleanups - RealTek (r8169): - add support for RTL8127ATF (10G Fiber SFP) - add dash and LTR support - Airoha: - AN8811HB 2.5 Gbps phy support - Freescale (fec): - add XDP zero-copy support - Thunderbolt: - add get link setting support to allow bonding - Renesas: - add support for RZ/G3L GBETH SoC - Ethernet switches: - Maxlinear: - support R(G)MII slow rate configuration - add support for Intel GSW150 - Motorcomm (yt921x): - add DCB/QoS support - TI: - icssm-prueth: support bridging (STP/RSTP) via the switchdev framework - Ethernet PHYs: - Realtek: - enable SGMII and 2500Base-X in-band auto-negotiation - simplify and reunify C22/C45 drivers - Micrel: convert bindings to DT schema - CAN: - move skb headroom content into skb extensions, making CAN metadata access more robust - CAN drivers: - rcar_canfd: - add support for FD-only mode - add support for the RZ/T2H SoC - sja1000: cleanup the CAN state handling - WiFi: - implement EPPKE/802.1X over auth frames support - split up drop reasons better, removing generic RX_DROP - additional FTM capabilities: 6 GHz support, supported number of spatial streams and supported number of LTF repetitions - better mac80211 iterators to enumerate resources - initial UHR (Wi-Fi 8) support for cfg80211/mac80211 - WiFi drivers: - Qualcomm/Atheros: - ath11k: support for Channel Frequency Response measurement - ath12k: a significant driver refactor to support multi-wiphy devices and and pave the way for future device support in the same driver (rather than splitting to ath13k) - ath12k: support for the QCC2072 chipset - Intel: - iwlwifi: partial Neighbor Awareness Networking (NAN) support - iwlwifi: initial support for U-NII-9 and IEEE 802.11bn - RealTek (rtw89): - preparations for RTL8922DE support - Bluetooth: - implement setsockopt(BT_PHY) to set the connection packet type/PHY - set link_policy on incoming ACL connections - Bluetooth drivers: - btusb: add support for MediaTek7920, Realtek RTL8761BU and 8851BE - btqca: add WCN6855 firmware priority selection feature" * tag 'net-next-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1254 commits) bnge/bng_re: Add a new HSI net: macb: Fix tx/rx malfunction after phy link down and up af_unix: Fix memleak of newsk in unix_stream_connect(). net: ti: icssg-prueth: Add optional dependency on HSR net: dsa: add basic initial driver for MxL862xx switches net: mdio: add unlocked mdiodev C45 bus accessors net: dsa: add tag format for MxL862xx switches dt-bindings: net: dsa: add MaxLinear MxL862xx selftests: drivers: net: hw: Modify toeplitz.c to poll for packets octeontx2-pf: Unregister devlink on probe failure net: renesas: rswitch: fix forwarding offload statemachine ionic: Rate limit unknown xcvr type messages tcp: inet6_csk_xmit() optimization tcp: populate inet->cork.fl.u.ip6 in tcp_v6_syn_recv_sock() tcp: populate inet->cork.fl.u.ip6 in tcp_v6_connect() ipv6: inet6_csk_xmit() and inet6_csk_update_pmtu() use inet->cork.fl.u.ip6 ipv6: use inet->cork.fl.u.ip6 and np->final in ip6_datagram_dst_update() ipv6: use np->final in inet6_sk_rebuild_header() ipv6: add daddr/final storage in struct ipv6_pinfo net: stmmac: qcom-ethqos: fix qcom_ethqos_serdes_powerup() ...
2026-02-04dt-bindings: phy: ti,control-phy-otghs: convert to DT schemaCharan Pedumuru
Convert TI OMAP Control PHY binding to DT schema. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Link: https://patch.msgid.link/20260123-ti-phy-v4-3-b557e2c46e6f@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-04dt-bindings: phy: ti,phy-usb3: convert to DT schemaCharan Pedumuru
Convert TI PIPE3 PHY binding to DT schema. Changes during conversion: - Define a new pattern 'pcie-phy' to match nodes defined in DT. - Drop obsolete "id" property from the schema. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260123-ti-phy-v4-2-b557e2c46e6f@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-28BackMerge tag 'v6.19-rc7' into drm-nextDave Airlie
Linux 6.19-rc7 This is needed for msm and rust trees. Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-01-22Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.19-rc7). Conflicts: drivers/net/ethernet/huawei/hinic3/hinic3_irq.c b35a6fd37a00 ("hinic3: Add adaptive IRQ coalescing with DIM") fb2bb2a1ebf7 ("hinic3: Fix netif_queue_set_napi queue_index input parameter error") https://lore.kernel.org/fc0a7fdf08789a52653e8ad05281a0a849e79206.1768915707.git.zhuyikai1@h-partners.com drivers/net/wireless/ath/ath12k/mac.c drivers/net/wireless/ath/ath12k/wifi7/hw.c 31707572108d ("wifi: ath12k: Fix wrong P2P device link id issue") c26f294fef2a ("wifi: ath12k: Move ieee80211_ops callback to the arch specific module") https://lore.kernel.org/20260114123751.6a208818@canb.auug.org.au Adjacent changes: drivers/net/wireless/ath/ath12k/mac.c 8b8d6ee53dfd ("wifi: ath12k: Fix scan state stuck in ABORTING after cancel_remain_on_channel") 914c890d3b90 ("wifi: ath12k: Add framework for hardware specific ieee80211_ops registration") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoCTommaso Merciai
Document USB2.0 phy bindings for RZ/G3E ("R9A09G047") SoC. The RZ/G3E USB2.0 phy is functionally identical to the one found on the RZ/V2H(P), so no driver changes are needed. The existing "renesas,usb2-phy-r9a09g057" will be used as a fallback compatible for this IP. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/4f2454708428b48e03faabe79e383999fb1ab458.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document mux-states propertyTommaso Merciai
Some Renesas SoCs, such as RZ/G3E, provide a USB2.0 OTG PHY with configurable VBUS control through a multiplexed hardware register. This register allows selecting the VBUS source via a mux control line exposed by the PHY. To represent this hardware configuration, support the standard `mux-states` property in the Renesas USB2 PHY binding. This allows the DeviceTree to model the VBUS source selection as a mux, consistent with generic binding conventions. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/36d448dd10bbb2bbfa5b1b6b6e3fee86c34d01aa.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulatorTommaso Merciai
Document the 'vbus-regulator' child node in the Renesas USB2 PHY binding to describe the internal USB VBUS regulator. Require this regulator node on OTG channels to accurately represent hardware dependencies in the device tree. Documenting this regulator allows device trees to model the VBUS power requirements of these SoCs properly. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/aaa8044283eb736817afd43d4fba3aa93b50b1dd.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Document extra clocks for MT8195Nícolas F. R. A. Prado
MT8195's HDMI PHY block has 4 clocks instead of just a single one. Describe the extra clocks for it. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-3-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Add support for MT8188 SoCLouis-Alexis Eyraud
Add compatible string for the HDMI PHY IP on MT8188 SoC, that is compatible with the one found on MT8195 SoC. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-2-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Fix clock output names for MT8195AngeloGioacchino Del Regno
For all of the HDMI PHYs compatible with the one found on MT8195 the output clock has a different datasheet name and specifically it is called "hdmi_txpll", differently from the older HDMI PHYs which output block is called "hdmitx_dig_cts". Replace clock output name string check by max item number one to allow the new name on all of the HDMI PHY IPs that are perfectly compatible with MT8195. [Louis-Alexis Eyraud: split patch, addressed previous feedback from mailing list, and reworded description] Fixes: c78fe548b062 ("dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-1-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-14dt-bindings: phy: google: Add Google Tensor G5 USB PHYRoy Luo
Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation (Laguna). The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Roy Luo <royluo@google.com> Link: https://patch.msgid.link/20251227-phyb4-v10-1-e8caf6b93fe7@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14Merge tag 'phy_common_properties' into nextVinod Koul
phy common properties Vladimir Oltean <vladimir.oltean@nxp.com> wrote: Introduce "rx-polarity" and "tx-polarity" device tree properties with Kunit tests
2026-01-14dt-bindings: phy-common-props: RX and TX lane polarity inversionVladimir Oltean
Differential signaling is a technique for high-speed protocols to be more resilient to noise. At the transmit side we have a positive and a negative signal which are mirror images of each other. At the receiver, if we subtract the negative signal (say of amplitude -A) from the positive signal (say +A), we recover the original single-ended signal at twice its original amplitude. But any noise, like one coming from EMI from outside sources, is supposed to have an almost equal impact upon the positive (A + E, E being for "error") and negative signal (-A + E). So (A + E) - (-A + E) eliminates this noise, and this is what makes differential signaling useful. Except that in order to work, there must be strict requirements observed during PCB design and layout, like the signal traces needing to have the same length and be physically close to each other, and many others. Sometimes it is not easy to fulfill all these requirements, a simple case to understand is when on chip A's pins, the positive pin is on the left and the negative is on the right, but on the chip B's pins (with which A tries to communicate), positive is on the right and negative on the left. The signals would need to cross, using vias and other ugly stuff that affects signal integrity (introduces impedance discontinuities which cause reflections, etc). So sometimes, board designers intentionally connect differential lanes the wrong way, and expect somebody else to invert that signal to recover useful data. This is where RX and TX polarity inversion comes in as a generic concept that applies to any high-speed serial protocol as long as it uses differential signaling. I've stopped two attempts to introduce more vendor-specific descriptions of this only in the past month: https://lore.kernel.org/linux-phy/20251110110536.2596490-1-horatiu.vultur@microchip.com/ https://lore.kernel.org/netdev/20251028000959.3kiac5kwo5pcl4ft@skbuf/ and in the kernel we already have merged: - "st,px_rx_pol_inv" - "st,pcie-tx-pol-inv" - "st,sata-tx-pol-inv" - "mediatek,pnswap" - "airoha,pnswap-rx" - "airoha,pnswap-tx" and maybe more. So it is pretty general. One additional element of complexity is introduced by the fact that for some protocols, receivers can automatically detect and correct for an inverted lane polarity (example: the PCIe LTSSM does this in the Polling.Configuration state; the USB 3.1 Link Layer Test Specification says that the detection and correction of the lane polarity inversion in SuperSpeed operation shall be enabled in Polling.RxEQ.). Whereas for other protocols (SGMII, SATA, 10GBase-R, etc etc), the polarity is all manual and there is no detection mechanism mandated by their respective standards. So why would one even describe rx-polarity and tx-polarity for protocols like PCIe, if it had to always be PHY_POL_AUTO? Related question: why would we define the polarity as an array per protocol? Isn't the physical PCB layout protocol-agnostic, and aren't we describing the same physical reality from the lens of different protocols? The answer to both questions is because multi-protocol PHYs exist (supporting e.g. USB2 and USB3, or SATA and PCIe, or PCIe and Ethernet over the same lane), one would need to manually set the polarity for SATA/Ethernet, while leaving it at auto for PCIe/USB 3.0+. I also investigated from another angle: what if polarity inversion in the PHY is one layer, and then the PCIe/USB3 LTSSM polarity detection is another layer on top? Then rx-polarity = <PHY_POL_AUTO> doesn't make sense, it can still be rx-polarity = <PHY_POL_NORMAL> or <PHY_POL_INVERT>, and the link training state machine figures things out on top of that. This would radically simplify the design, as the elimination of PHY_POL_AUTO inherently means that the need for a property array per protocol also goes away. I don't know how things are in the general case, but at least in the 10G and 28G Lynx SerDes blocks from NXP Layerscape devices, this isn't the case, and there's only a single level of RX polarity inversion: in the SerDes lane. In the case of PCIe, the controller is in charge of driving the RDAT_INV bit autonomously, and it is read-only to software. So the existence of this kind of SerDes lane proves the need for PHY_POL_AUTO to be a third state. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-5-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy-common-props: ensure protocol-names are uniqueVladimir Oltean
Rob Herring points out that "The default for .*-names is the entries don't have to be unique.": https://lore.kernel.org/linux-phy/20251204155219.GA1533839-robh@kernel.org/ Let's use uniqueItems: true to make sure the schema enforces this. It doesn't make sense in this case to have duplicate properties for the same SerDes protocol. Note that this can only be done with the $defs + $ref pattern as established by the previous commit. When the tx-p2p-microvolt-names constraints were expressed directly under "properties", it would have been validated by the string-array meta-schema, which does not support the 'uniqueItems' keyword as can be seen below. properties:tx-p2p-microvolt-names: Additional properties are not allowed ('uniqueItems' was unexpected) from schema $id: http://devicetree.org/meta-schemas/string-array.yaml Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-4-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy-common-props: create a reusable "protocol-names" definitionVladimir Oltean
Other properties also need to be defined per protocol than just tx-p2p-microvolt-names. Create a common definition to avoid copying a 55 line property. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-3-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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